Advertisement

Charge Plasma Based Bipolar Junction Transistor on Silicon on Insulator

  • Sajad A. Loan
  • Faisal Bashir
  • Asim. M. Murshid
  • Humyra Shabir
  • M. Rafat
  • M. Nizamuddin
  • Abdul Rahman Alamoud
  • Shuja A. Abbasi
Chapter

Abstract

Charge plasma based devices are gaining interest due to various reasons, since these devices doesn’t require conventional ways of creating different doping regions, therefore these devices are free from various doping related issues related, as random doping fluctuations, doping activations and the requirement of high temperature annealing are absent in these devices. In this work we put forward a novel lateral pnp bipolar transistor on silicon on insulator. Metals of different work function are used to induce n and p type charge plasma on undoped silicon to have emitter, base and collector regions. The 2D simulation study has revealed that a very high current gain is achieved in the proposed device in comparison to conventional pnp transistor. The charge plasma concept is very much appropriate in surmounting the doping related issues such as diffusion or ion implantation, random doping fluctuations and high thermal budget in current nano devices.

Keywords

Charge plasma Current gain Doping Lateral BJT SOI Work function 

Notes

Acknowledgments

This work was supported by NSTIP strategic technologies programs number (11-NAN-2118-02) in the Kingdom Saudi Arabia.

References

  1. 1.
    A. Tamba, T. Someya, T. Sakagami, N. Akiyama, Y. Kobayashi, CMOS-compatible lateral bipolar transistor for BiCMOS technology. II. Experimental results. IEEE Trans. Electron Devices 39, 1865–1869 (1992)CrossRefGoogle Scholar
  2. 2.
    V.M.C. Chen, J.C.S. Woo, A low thermal budget, fully self-aligned lateral BJT on thin film SOI substrate for low power BiCMOS applications, in Symposium on VLSI Technology Digest of Technical Papers, June 1995, pp. 133–134Google Scholar
  3. 3.
    T.H. Ning, Why BiCMOS and SOI BiCMOS. IBM J. Res. Dev. 46, 181–186 (2002)CrossRefMathSciNetGoogle Scholar
  4. 4.
    K. Washio, SiGe HBT and BiCMOS technologies for optical transmission and wireless communication systems. IEEE Trans. Electron Devices 50, 656–658 (2003)CrossRefGoogle Scholar
  5. 5.
    S.A. Loan et al., A high performance charge plasma PN-Schottky collector transistor on silicon-on-insulator. Semicond. Sci. Technol. 29(9), 095001, 9pp (2014).CrossRefGoogle Scholar
  6. 6.
    R. Bashir et al., A complementary bipolar technology family with a vertically integrated PNP for high-frequency analog applications. IEEE Trans. Electron Devices 48(11), 2525–2534 (2001)CrossRefGoogle Scholar
  7. 7.
    M. Mitchell, S. Nigrin, F. Cristiano, P. Ashburn, P. Hemment, Characterization of NPN and PNP SiGe hetero-junction bipolar transistors formed by Ge+ implantation, in Symposium on High Performance Electron Devices for Microwave Optoelectronics, pp. 254–259 (1999)Google Scholar
  8. 8.
    Q. Quyang, J. Cai, T.H. Ning, J.B. Johnson, A simulation study on thin SOI bipolar transistors with fully or partially depleted collector. IEEE BCTM 1, 28–31 (2002)Google Scholar
  9. 9.
    S.A. Loan, S. Qureshi, S.S.K. Iyer, A novel high breakdown voltage lateral bipolar transistor on SOI with multizone doping and multistep oxide. Semicond. Sci. Technol. 24(2), 025017, 10pp (2009).CrossRefGoogle Scholar
  10. 10.
    J. Cai, T.H. Ning, Bipolar transistor on thin SOI: concept, status and prospect, in Proceedings of IEEE International Conference on Solid State and IC Technology, pp. 2102–2107 (2004)Google Scholar
  11. 11.
    I.H.M. Sun, W.T. Ng, K. Kanekiyo, T. Kobayashi, H. Mochizuki, M. Toita et al., Lateral high speed bipolar transistors on SOI for RF SoC applications. IEEE Trans. Electron Devices 52, 1376–1383 (2005)CrossRefGoogle Scholar
  12. 12.
    H. Ni, T. Yamada, K. Inoh, T. Shino, S. Kawanaka, M. Yoshimi, Y. Katsumata, A novel lateral bipolar transistor with 67 GHz f(max) on thin-film SOI for RF analog applications. IEEE Trans. Electron Devices 47(7), 1536–1541 (2000)CrossRefGoogle Scholar
  13. 13.
    S.A. Loan, S. Qureshi, S.S.K. Iyer, A novel partial ground plane based MOSFET on selective buried oxide: 2D simulation study. IEEE Trans. Electron Devices 57(3), 1–10 (2010)CrossRefGoogle Scholar
  14. 14.
    B. Rajasekharan, C. Salm, R.J.E. Hueting, T. Hoang, J. Schmitz, The charge plasma p-n diode. IEEE Electron Device Lett. 29(12), 1367–1369 (2008)CrossRefGoogle Scholar
  15. 15.
    B. Rajasekharan, R.J.E. Hueting, C. Salm, T. van Hemert, R.A.M. Wolters, J. Schmitz, Fabrication and characterization of the charge-plasma diode. IEEE Electron Device Lett. 31(6), 528–530 (2010)CrossRefGoogle Scholar
  16. 16.
    M.J. Kumar, K. Nadda, Bipolar charge-plasma transistor: a novel three terminal device. IEEE Trans. Electron Devices 59(4), 962–967 (2012)CrossRefGoogle Scholar
  17. 17.
    S.A. Loan et al., A high performance charge plasma based lateral bipolar transistor on selective buried oxide. Semicond. Sci. Technol. 29, 015011 (2014). (10pp)Google Scholar
  18. 18.
    ATLAS, Device Simulation Software (Silvaco Int, Santa Clara, 2010)Google Scholar
  19. 19.
    A. Asenov et al., Random dopant induced threshold voltage lowering and fluctuations in sub 50 nm MOSFETs: a statistical 3D atomistic’ simulation study. Nanotechnology 10, 153–158 (1999)CrossRefGoogle Scholar
  20. 20.
    F. Bashir, S.A. Loan, M. Nizamuddin, H. Shabir, A.M. Murshid, M. Rafat, A.R.M. Alamoud, S.A. Abbasi, A novel high performance nanoscaled dopingless lateral PNP transistor on silicon on insulator, in Proceedings of the International Multiconference of Engineers and Computer Scientists 2014, IMECS 2014, Hong Kong, 12–14 Mar 2014. Lecture Notes in Engineering and Computer Science, pp. 679–682Google Scholar
  21. 21.
    D.B.M. Klassen, A unified mobility model for device simulation—I: model equations and concentration dependence. Solid State Electron. 35(7), 953–959 (1992)CrossRefGoogle Scholar
  22. 22.
    D.B.M. Klaassen, J.W. Slotboom, H.C. De Graaff, Unified apparent band-gap narrowing in n- and p-type silicon. Solid State Electron. 35(2), 125–129 (1992)CrossRefGoogle Scholar
  23. 23.
    D.B.M. Klassen, A unified mobility model for device simulation—II: temperature dependence of carrier mobility and lifetime. Solid State Electron. 35(7), 961–967 (1992)CrossRefGoogle Scholar
  24. 24.
    S. Selberherr, Analysis and Simulation of Semiconductor Devices (Springer, Wien, 1984)CrossRefGoogle Scholar
  25. 25.
    M. Shirahata, H. Kusano, N. Kotani, S. Kusanoki, Y. Akasaka, A mobility model including the screening effect in MOS inversion layer. IEEE Trans. Comput. Aided Design Integr. Circuits Syst. 11(9), 1114–1119 (1992)CrossRefGoogle Scholar
  26. 26.
    M.J. Kumar, V. Parihar, Surface accumulation layer transistor (SALTran): a new bipolar transistor for enhanced current gain and reduced hot-carrier degradation. IEEE Trans. Device Mater. Rel. 4(3), 509–515 (2004)CrossRefGoogle Scholar
  27. 27.
    M.J. Kumar, P. Singh, A super beta bipolar transistor using SiGe base surface accumulation layer transistor (SALTran) concept: a simulation study. IEEE Trans. Electron Devices 53(3), 577–579 (2006)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2015

Authors and Affiliations

  • Sajad A. Loan
    • 1
  • Faisal Bashir
    • 1
  • Asim. M. Murshid
    • 2
  • Humyra Shabir
    • 4
    • 5
  • M. Rafat
    • 5
  • M. Nizamuddin
    • 1
  • Abdul Rahman Alamoud
    • 3
  • Shuja A. Abbasi
    • 3
  1. 1.Department of Electronics and Communication EngineeringJamia Millia IslamiaNew DelhiIndia
  2. 2.Department of Computer SciencesKirkuk UniversityKirkukIraq
  3. 3.Department of Electrical EngineeringKing Saud UniversityRiyadhSaudi Arabia
  4. 4.Department of Electronics EngineeringJamia Millia IslamiaNew DelhiIndia
  5. 5.Department of Applied SciencesJamia Millia IslamiaNew DelhiIndia

Personalised recommendations