PVT Insensitive IREF Generation

  • Suhas Vishwasrao ShindeEmail author


In this paper, supply, process and temperature compensated, low voltage current reference for CMOS integrated circuits is presented. To minimize production cost, it uses no BJTs, external components or trimming procedures. This circuit is designed in Intel-22nm process and evaluated by computer simulations. The circuit behaviour is supported by theoretical expressions and is in agreement with simulation results. A comparison with most current references in the literature shows considerable tolerance improvement. Simulation results show PVT tolerance of ±10 % and 1σ standard deviation of 5 μA at mean of 82 μA. An autonomous, all MOS, low voltage and process technology independent features make it suitable for advanced sub micron processes like 14, 10 nm and beyond.


BGR CTAT PTAT Sub threshold Strong inversion Weak inversion 



The author wishes to thank Intel Microelectronics for providing necessary access to tools and Intel 22nm process technology.


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Copyright information

© Springer Science+Business Media Dordrecht 2015

Authors and Affiliations

  1. 1.Intel Mobile Communications, GmbHNeubibergGermany

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