TSV Decoupling Schemes

  • Eunseok Song
  • Jun So Pak
  • Joungho Kim


Three-dimensional (3D) through silicon via (TSV) technologies promise increased system integration at lower cost and reduced footprint, as well as increased system bandwidth. Three-dimensional TSV may be implemented by simply adapting current silicon fabrication and package technologies. There is a strong demand for 3D, high-density and the heterogeneous integration of silicon and passive components because 3D integrated circuit (3D ICs) increase layout complexity due to the needs for additional solution space, as well as increased power density and power noise issues. To overcome the I/O speed limitation related to the above power problems in 3D ICs, on-chip decoupling capacitors and passive components used in the packaging have been implemented using TSV technologies. In this chapter, TSV decoupling schemes are introduced, showing that they have prominent advantages relative to reducing the inductive power distribution network (PDN) impedance and suppressing power noise such as the simultaneously switching noise (SSN) in the 3D ICs.


3D integrated circuit Decoupling capacitor Decoupling capacitor stacked chip Deep trench (DT) capacitor Low equivalent series inductance Off-chip discrete decoupling capacitor On-chip NMOS capacitor Power distribution network Power/ground noise Power integrity Self-impedance (Z11Stacking Simultaneous switching noise Through-silicon-via 


  1. 1.
    Dang B, Shapiro M, Andry P, Tsang C, Sprogis E, Wright S, Interrante M, Griffith J, Truong V, Guerin L, Liptak R, Berger D, Knickerbocker J (2010) Three-dimensional chip stack with integrated decoupling capacitors and Thru-Si via interconnects. IEEE Electron Dev Lett 31(12):1461–1463Google Scholar
  2. 2.
    Hwei Ng C, Ho C-S, Sanford Chu S-F, Sun S-C (2005) MIM capacitor integration for mixed-signal/RF applications. IEEE Trans Electron Dev 52(7):1399–14092CrossRefGoogle Scholar
  3. 3.
    Rius J, Meijer M (2009) Analysis of the influence of substrate on the performance of on-chip MOS decoupling capacitors. IEEE J Solid-State Circuits 44(2):484–494CrossRefGoogle Scholar
  4. 4.
    Jayaraman B, Gupta S, Zhang Y, Goyal P, Ho H, Krishnan R, Fang S, Lee S, Daley D, McStay K, Wunder B, Barth J, Deshpande S, Parries P, Malik P, Agnello P, Stiffler S, Iyer SS (2012) Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond. In: IEEE international conference on IC design & technology (ICICDT)Google Scholar
  5. 5.
    Muthana P, Srinivasan K, Ege Engin A, Swaminathan M, Tummala R, Sundaram V, Wiedenman B, Amey DI, Dietz KH, Banerji S (2008) Improvements in noise suppression for I/O circuits using embedded planar capacitors. IEEE Trans Adv Packag 31(2):234–245Google Scholar
  6. 6.
    Cheng H-H, Kuo C-W, Pan P-C, Chen Y-H, Chen K-H, Li L, Han K, Cooper G (2011) Design and characterization of power delivery system for multi-chip package with embedded discrete capacitors. In: Electronic components and technology conference (ECTC), 31 May–3 June 2011, pp 2179–2184Google Scholar
  7. 7.
    Charania T, Opal A, Sachdev M (2012) Analysis and design of on-chip decoupling capacitors. IEEE Trans Very Large Scale Integr Syst 21(4):648–658Google Scholar
  8. 8.
    Roberts D et al (2005) Application of on-chip MIM decoupling capacitor for 90 nm SOI microprocessor. In: IEEE international electron devices meeting (IEDM), pp 72–75Google Scholar
  9. 9.
    Sanchez H et al (2006) Increasing microprocessor speed by massive application of on-die high-K MIM decoupling capacitors. In: IEEE international solid-state circuits conference (ISSCC), pp 2190–2199Google Scholar
  10. 10.
    Zhen C, Lihui G, Mingbin Y, Yi Z (2002) A study of MIMIM on-chip capacitor using Cu/SiO2 interconnect technology. IEEE Microw Wirel Compon Lett 12(7):246–248Google Scholar
  11. 11.
    Zhao X, Minz J, Lim SK (2011) Low-power and reliable clock network design for through-silicon via (TSV) based 3D ICs. IEEE Trans Compon Packag Manuf Technol 1(2):247–259CrossRefGoogle Scholar
  12. 12.
    JS Pak, J Kim, J Cho, K Kim, T Song, S Ahn, J Lee, H Lee, K Park, J Kim, PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P/G TSV Array Model Based on Separated P/G TSV and Chip-PDN Models. IEEE Trans Compon Packag Manuf Technol 1(2):208–219Google Scholar
  13. 13.
    Cho J et al (2011) Modeling and analysis of through-silicon-via (TSV) noise coupling and suppression using a guard ring. IEEE Trans Compon Packag Manuf Technol 1(2):220–233CrossRefGoogle Scholar
  14. 14.
    Xie J, Swaminathan Mn (2011) Electrical-thermal co-simulation of 3D integrated systems with micro-fluidic cooling and joule heating effects. IEEE Trans Compon Packag Manuf Technol 1(2):234–246CrossRefGoogle Scholar
  15. 15.
    Wang X-P, Yin W-Y, He S (2010) Multiphysics characterization of transient electrothermomechanical responses of through-silicon vias applied with a periodic voltage pulse. IEEE Trans Electron Devices 57(6):1382–1389CrossRefGoogle Scholar
  16. 16.
    Van der Plas G et al (2011) Design issues and considerations for low-cost 3-D TSV IC technology. IEEE J Solid-State Circuits 46(1):293–307CrossRefGoogle Scholar
  17. 17.
    Kang U, Chung H, Heo S, Park D, Lee H, Kim J, Ahn S, Cha S, Ahn J, Kwon D, Lee J, Joo H, Kim W, Jang D, Kim N, Choi J, Chung T, Yoo J, Choi J, Kim C, Jun Y (2010) 8 Gb 3-D DDR3 DRAM using through-silicon-via technology. IEEE J Solid-State Circuits 45(1):111–119Google Scholar
  18. 18.
    Ahmad W, Zheng L-R, (Member) Chen Q, Tenhunen H (2011) Peak-to-peak ground noise on a power distribution TSV pair as a function of rise time in 3-D stack of dies interconnected through TSVs. IEEE Trans Compon Packag Manuf Technol 1(2):196–207Google Scholar
  19. 19.
    Ryu Chunghyun, Park Jiwoon, Pak JS, Lee K, Oh T, Kim J (2007) Suppression of power/ground inductive impedance and simultaneous switching noise using silicon through-via in a 3-D stacked chip package. IEEE Microwave Wirel Compon Lett 17(12):855–857CrossRefGoogle Scholar
  20. 20.
    Hobbs JM, Windlass H, Sundaram V, Chun S, White GE, Swaminathan M, Tummala RR (2001) Simultaneous switching noise suppression for high speed systems using embedded decoupling. In: Electronic components and technology conference (ECTC), pp 339–343Google Scholar
  21. 21.
    Popovich M, Sotman M, Kolodny A, Friedman EG (2008) Effective radii of on-chip decoupling capacitors. IEEE Trans Very Large Scale Integr Syst (VLSI) 16(7):894–907Google Scholar
  22. 22.
    Muthana P, Engin AE, Swaminathan M, Tummala R, Sundaram V, Wiedenman B, Amey D, Dietz KH, Banerji S (2007) Design, modeling, and characterization of embedded capacitor networks for core decoupling in the package. IEEE Trans Adv Packag 30(4):809–822Google Scholar
  23. 23.
    Raj PM, Balaraman D, Govind V, Abothu IR, Wan L, Gerhardt R, Swaminathan M, Tummala R (2007) Processing and dielectric properties of nanocomposite thin film “Supercapacitors” for high-frequency embedded decoupling. IEEE Trans Compon Packag Manuf Technol 30(4):569–578Google Scholar
  24. 24.
    Wu T-L, Chuang H-H, Wang T-K (2010) Overview of power integrity solutions on package and PCB: decoupling and EBG isolation. IEEE Trans Electromagn Compat 52(2):346–356CrossRefGoogle Scholar
  25. 25.
    Song E, Koo K, Kim J, Pak JS (2013) Through-silicon-via-based decoupling capacitor stacked chip in 3-D-ICs. IEEE Trans Compon Packag Manuf Technol (CPMT) 3(9):1467–1480Google Scholar
  26. 26.
    Lim SK (2005) Physical design for 3D system on package. IEEE Design Test Comput 22(6):532–539Google Scholar
  27. 27.
    Kim J et al (2010) Chip-package hierarchical power distribution network modeling and analysis based on a segmentation method. IEEE Trans Adv Packag 33(3):647–659Google Scholar
  28. 28.
    Kim J et al (2011) High-frequency scalable electrical model and analysis of a through silicon via (TSV). IEEE Trans Compon Packag Manuf Technol 1(2):181–195CrossRefGoogle Scholar
  29. 29.
    Larsson P (1997) Parasitic resistance in an MOS transistor used as on-chip decoupling capacitance. IEEE J Solid-State Circuits 32(4):574–576CrossRefMathSciNetGoogle Scholar
  30. 30.
    Song E, Pak JS, Kim J (2012) TSV-based decoupling capacitor schemes in 3DIC. In: Proceedings of the 62nd electronic components and technology conference (ECTC), San Diego, CA, 29 May 2012Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2014

Authors and Affiliations

  1. 1.Department of Electrical EngineeringKAISTDaejeonRepublic of Korea
  2. 2.System LSISamsung Electronics Co., Ltd.HwaseongRepublic of Korea

Personalised recommendations