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TSV Decoupling Schemes

  • Eunseok Song
  • Jun So Pak
  • Joungho Kim
Chapter

Abstract

Three-dimensional (3D) through silicon via (TSV) technologies promise increased system integration at lower cost and reduced footprint, as well as increased system bandwidth. Three-dimensional TSV may be implemented by simply adapting current silicon fabrication and package technologies. There is a strong demand for 3D, high-density and the heterogeneous integration of silicon and passive components because 3D integrated circuit (3D ICs) increase layout complexity due to the needs for additional solution space, as well as increased power density and power noise issues. To overcome the I/O speed limitation related to the above power problems in 3D ICs, on-chip decoupling capacitors and passive components used in the packaging have been implemented using TSV technologies. In this chapter, TSV decoupling schemes are introduced, showing that they have prominent advantages relative to reducing the inductive power distribution network (PDN) impedance and suppressing power noise such as the simultaneously switching noise (SSN) in the 3D ICs.

Keywords

3D integrated circuit Decoupling capacitor Decoupling capacitor stacked chip Deep trench (DT) capacitor Low equivalent series inductance Off-chip discrete decoupling capacitor On-chip NMOS capacitor Power distribution network Power/ground noise Power integrity Self-impedance (Z11Stacking Simultaneous switching noise Through-silicon-via 

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Copyright information

© Springer Science+Business Media Dordrecht 2014

Authors and Affiliations

  1. 1.Department of Electrical EngineeringKAISTDaejeonRepublic of Korea
  2. 2.System LSISamsung Electronics Co., Ltd.HwaseongRepublic of Korea

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