An Efficient Embedded System for the Detection and Recognition of Speed-Limit Signs

  • Hsing-Lung Chen
  • Ming-Sze Chen
  • Shu-Hua Hu
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 301)


This paper is aimed at detecting and recognizing speed-limit signs in real-time. The recognition of speed-limit signs gives the necessary reminders and warnings to the drivers who may ignore the speed-limit signs. In the previous literatures, most of proposed schemes for real-time detection and recognition of traffic signs employed the software approach. It not only needs a large amount of data processing, but also requires a high demand of hardware. Therefore, we propose a hardware-software co-design scheme on FPGA, where regular computations are executed in parallel with hardware, resulting in detecting and recognizing speed-limit signs in real-time. The experiments show that our proposed scheme can detect and recognize a speed-limit sign in 62.558 ms. The detection rate is about 99 %. And the recognition rate is 100 %.



This work was support, in part, by National Science Council, Republic of China, under Grant No. NSC 102-2221-E-011-067.


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Copyright information

© Springer Science+Business Media Dordrecht 2014

Authors and Affiliations

  1. 1.Department of Electronic and Computer EngineeringNational Taiwan University of Science and TechnologyTaipeiTaiwan
  2. 2.Department of Computer Science and Information EngineeringJinwen University of Science and TechnologyNew TaipeiTaiwan

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