Abstract
NoC architecture has been increasingly applied to complex SoC chips and how to efficiently map the specific application to NoC infrastructure is an important topic urgently needed to study for NoC. At the same time, there are many challenges for NoC embedded IP cores testing. This paper proposes a sectional NoC mapping algorithm optimized for NoC IP cores testing. Associated with the pre-designed test structure, sectional NoC mapping firstly adapts the Partition Algorithm to arrange IP cores into parallel testing groups to minimize testing time. Then, it applies genetic algorithm for NoC mapping based on the traffic information between IP cores. The experiment results on ITC’02 benchmark circuits showed that the mapping costs decreased by 24.5 % on average compared with the random mapping and the testing time can be reduced by 12.67 % on average as well, which illustrated the effectiveness of the sectional NoC mapping scheme.
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Acknowledgment
This work was supported by the Natural Science Foundation of China under Grant 61076019, 61106018 and 61376025, the Aeronautical Science Foundation of China under Grant 20140652008, Prospective joint research project of on the Integration of Industry, Education and Research of Jiangsu Province 2014003-05.
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Ying, Z., Ning, W., Fen, G. (2015). Sectional NoC Mapping Scheme Optimized for Testing Time. In: Kim, H., Amouzegar, M., Ao, Sl. (eds) Transactions on Engineering Technologies. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7236-5_21
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DOI: https://doi.org/10.1007/978-94-017-7236-5_21
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