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Part of the book series: NATO ASI Series ((NSSE,volume 48))

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Abstract

This section discusses the basic facts of design for testability. A short review of testing is given along with some reasons why one should test. The different techniques of design for testability are discussed in detail. These include techniques which can be applied to today’s technologies and techniques which have been recently introduced and will soon appear in new designs.

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General References and Surveys

  1. Breuer, M. A., (ed.), Diagnosis and Reliable Design of Digital Systems, Computer Science Press, 1976.

    Google Scholar 

  2. Chang, H. Y., E. G. Manning, and G. Metze, Fault Diagnosis of Digital Systems, Wiley Interscience, N.Y., 1970.

    MATH  Google Scholar 

  3. Friedman, A. D., and P. R. Menon, Fault Detection in Digital Circuits, Prentice Hall, New Jersey, 1971.

    Google Scholar 

  4. Hennie, F. C., Finite State Models for Logical Machines, J. Wiley & Sons, N. Y., 1968.

    MATH  Google Scholar 

  5. Kovijanic, P. G., “A New Look at Test Generation and Verification,” Proc. 14th Design Automation Conference, June 1977, 77CH1216–1C, pp. 58–63.

    Google Scholar 

  6. Muehldorf, E. I., “Designing LSI Logic for Testability,” Digest of Papers, 1976 Annl. Semiconductor Test Symp., Oct. 1976, 76CH1179–1C, pp. 45–49.

    Google Scholar 

  7. Susskind, A. K., “Diagnostics for Logic Networks,” IEEE Spectrum, Oct. 1973, pp 40–47.

    Google Scholar 

  8. Williams, T. W., and K. P. Parker, “Testing Logic Networks and Design for Testability,” Computer, Oct. 1979, pp. 9–21.

    Google Scholar 

  9. IEEE Standard Dictionary of Electrical and Electronics Terms, IEEE Inc., Wiley Interscience, N. Y., 1972.

    Google Scholar 

References on Designing for Testability

  1. “A Designer’s Guide to Signature Analysis,” Hewlett Packard Application Note 222, Hewlett Packard, 5301 Stevens Creek Blvd., Santa Clara, CA 95050.

    Google Scholar 

  2. Akers, S. B., “Partitioning for Testability,” Journal of Design Automation & Fault-Tolerant Computing, Vol. 1, No. 2, Feb. 1977.

    Google Scholar 

  3. Ando, H., “Testing VLSI with Random Access Scan,” Digest of Papers Compcon 80, Feb. 1980, 80CH1491-OC, pp. 50–52.

    Google Scholar 

  4. Bottorff, P., and E. I. Muehldorf, “Impact of LSI on Complex Digital Circuit Board Testing,” Electro 77, New York, N.Y., April, 1977.

    Google Scholar 

  5. DasGupta, S., E. B. Eichelberger, and T. W. Williams, “LSI Chip Design for Testability,” Digest of Technical Papers, 1978 International Solid-State Circuits Conference, San Francisco, Feb., 1978, pp. 216–217.

    Google Scholar 

  6. “Designing Digital Circuits for Testability,” Hewlett Packard Application Note 210–4, Hewlett Packard, Loveland, CO 80537.

    Google Scholar 

  7. Eichelberger, E. B., and T. W. Williams, “A Logic Design Structure for LSI Testability,” Journal of Design Automation & Fault-Tolerant Computing, Vol 2., No. 2, May 1978, pp. 165–178.

    Google Scholar 

  8. Eichelberger, E. B., and T. W. Williams, “A Logic Design Structure for LSI Testing,” Proc. 14th Design Automation Conf., June 1977, 77CH1216–1C, pp. 462–468.

    Google Scholar 

  9. Eichelberger, E. B., E. J. Muehldorf, R. G. Walter, and T. W. Williams, “A Logic Design Structure for Testing Internal Arrays,” Proc. 3rd USA-Japan Computer Conference, San Francisco, Oct. 1978, pp. 266–272.

    Google Scholar 

  10. Funatsu, S., N. Wakatsuki, and T. Arima, “Test Generation Systems in Japan,” Proc. 12th Design Automation Symp., June 1975, pp. 114–22.

    Google Scholar 

  11. Godoy, H. C., G. B. Franklin, and P. S. Bottoroff, “Automatic Checking of Logic Design Structure for Compliance with Testability Groundrules,” Proc. 14th Design Automation Conf., June 1977, 77CH1216–1C, pp. 469–478.

    Google Scholar 

  12. Hayes, J. P., “On Modifying Logic Networks to Improve their Diagnosability,” IEEE-TC, Vol. C-23, Jan. 1974, pp. 56–62.

    MathSciNet  Google Scholar 

  13. Hayes, J. P., and A. D. Friedman, “Test Point Placement to Simplify Fault Detection,” FTC-3, Digest of Papers, 1973 Symposium on Fault-Tolerant Computing, June 1973, pp. 73–78.

    Google Scholar 

  14. Koenemann, B., J. Mucha, and G. Zwiehoff, “Built-In Logic Block Observation Techniques,” Digest of Papers, 1979 Test Conference, Oct. 1979, 79CH1509–9C, pp. 37–41.

    Google Scholar 

  15. Lippman, M. D., and E. S. Donn, “Design Forethought Promotes Easier Testing of Microcomputer Boards,” Electronics, Jan. 18, 1979, pp. 113–119.

    Google Scholar 

  16. Nadig, H. J., “Signature Analysis-Concepts, Examples, and Guidelines,” Hewlett Packard Journal, May 1977, pp. 15–21.

    Google Scholar 

  17. Neil, M., and R. Goodner, “Designing a Serviceman’s Needs into Microprocessor Based Systems,” Electronics, March 1, 1979, pp. 122–128.

    Google Scholar 

  18. Stewart, J. H., “Future Testing of Large LSI Circuit Cards,” Digest of Papers 1977 Semiconductor Test Symp., Oct. 1977, 77CH1261–7C, pp. 6–17.

    Google Scholar 

  19. Toth, A., and C. Holt, “Automated Data Base-Driven Digital Testing,” Computer, Jan. 1974, pp. 13–19.

    Google Scholar 

  20. White, E., “Signature Analysis, Enhancing the Serviceability of Microprocessor-Based Industrial Products,” Proc. 4th IECI Annual Conference, March 1978, 78CH1312–8, pp. 68–76.

    Google Scholar 

  21. Williams, M. J. Y., and J. B. Angelí, “Enhancing Testability of Large Scale Integrated Circuits via Test Points and Additional Logic,” IEEE-TC, Vol. C-22, Jan. 1973, pp. 46–60.

    Google Scholar 

  22. Williams, T. W., “Utilization of a Structured Design for Reliability & Serviceability,” Digest, Government Microcircuits Applications Conference, Monterey, Calif., Nov. 1978, pp. 441–444.

    Google Scholar 

References on Faults and Fault Modeling

  1. Boute, R., and E. J. McCluskey, “Fault Equivalence in Sequential Machines,” Proc. Symp. on Computers and Automata, Polytechnic Inst, of Brooklyn, April 13–15, 1971, pp. 483–507.

    Google Scholar 

  2. Boute, R. T., “Optimal and Near-Optimal Checking Experiments for Output Faults in Sequential Machines,” IEEE-TC, Vol.C-23, No. 11, Nov. 1974, pp. 1207–1213.

    Google Scholar 

  3. Boute, R. T., “Equivalence and Dominance Relations Between Output Faults in Sequential Machines,” Tech. Report No. 38, SU-SEL-72–052, Nov. 1972, Stanford University, Stanford, Calif.

    Google Scholar 

  4. Dias, F. J. O., “Fault Masking in Combinational Logic Circuits,” IEEE-TC, Vol. C-24, May 1975, pp. 476–482.

    Google Scholar 

  5. Hayes, J. P., “A NAND Model for Fault Diagnosis in Combinational Logic Networks,” IEEE-TC, Vol. C-20, Dec. 1971, pp. 1496–1506.

    MathSciNet  Google Scholar 

  6. McCluskey, E. J., and F. W. Clegg, “Fault Equivalence in Combinational Logic Networks,” IEEE-TC, Vol. C-20, Nov. 1971, pp. 1286–1293.

    MathSciNet  Google Scholar 

  7. Mei, K. C. Y., “Fault Dominance in Combinational Circuits,” Technical Note No. 2, Digital Systems Laboratory, Stanford University, Aug. 1970.

    Google Scholar 

  8. Mei, K. C. Y., “Bridging and Stuck-At Faults,” IEEE-TC, Vol. C-23, No. 7, July 1974, pp. 720–727.

    Google Scholar 

  9. Ogus, R. C., “The Probability of a Correct Output from a combinational Circuit,” IEEE-TC, Vol. C-24, No. 5, May 1975, pp. 534–544.

    MathSciNet  Google Scholar 

  10. Parker, K. P., and E. J. McCluskey, “Analysis of Logic Circuits with Faults Using Input Signal Probabilities,” IEEE-TC, Vol. C-24, No. 5, May 1975, pp. 573–578.

    Google Scholar 

  11. Schertz, D. R., and D. G. Metze, “A New Representation for Faults in Combinational Digital Circuits,” IEEE-TC, Vol. C-21, No. 8, Aug. 1972, pp. 858–866.

    Google Scholar 

  12. Shedletsky, J. J., and E. J. McCluskey, “The Error Latency of a Fault in a Sequential Digital Circuit,” IEEE-TC, Vol. C-25, No. 6, June 1976, pp. 655–659.

    MathSciNet  Google Scholar 

  13. Shedletsky, J. J., and E. J. McCluskey, “The Error Latency of a Fault in a Combinational Digital Circuit,” FTCS-5, Digest of Papers, Fifth International Symposium on Fault Tolerant Computing, Paris, France, June 1975, pp. 210–214.

    Google Scholar 

  14. To, K., “Fault Folding for Irredundant and Redundant Combinational Circuits,” IEEE-TC, Vol. C-22, No. 11, Nov. 1973, pp. 1008–1015.

    Google Scholar 

  15. Wang, D. T., “Properties of Faults and Criticalities of Values Under Tests for Combinational Networks,” IEEE-TC, Vol. C-24, No. 7, July 1975, pp. 746–750.

    Google Scholar 

References on Testing and Fault Location

  1. Batni, R. P., and C. R. Kime, “A Module Level Testing Approach for Combinational Networks,” IEEE-TC, Vol. C-25, No. 6, June 1976, pp. 594–604.

    Google Scholar 

  2. Bisset, S., “Exhaustive Testing of Microprocessors and Related Devices: A Practical Solution,” Digest of Papers, 1977 Semiconductor Test Symp., Oct. 1977, pp. 38–41.

    Google Scholar 

  3. Czepiel, R. J., S. H. Foreman, and R. J. Prilik, “System for Logic, Parametric and Analog Testing,” Digest of Papers, 1976 Semiconductor Test Symp., Oct. 1976, pp. 54–69.

    Google Scholar 

  4. Frohwerk, R. A., “Signature Analysis: A New Digital Field Service Method,” Hewlet Packard Journal, May 1977, pp. 2–8.

    Google Scholar 

  5. Gimmer, B. A., “Test Techniques for Circuit Boards Containing Large Memories and Microprocessors,” Digest of Papers, 1976 Semiconductor Test Symp., Oct. 1976, pp. 16–21.

    Google Scholar 

  6. Groves, W. A., “Rapid Digital Fault Isolation with FASTRACE,” Hewlett Packard Journal, March 1979, pp. 8–13.

    Google Scholar 

  7. Hayes, J. P., “Rapid Count Testing for Combinational Logic Circuits,” IEEE-TC, Vol. C-25, No. 6, June 1976, pp. 613–620.

    Google Scholar 

  8. Hayes, J. P., “Detection of Pattern Sensitive Faults in Random Access Memories,” IEEE-TC, Vol. C-24, No. 2, Feb. 1975, pp. 150–160.

    MathSciNet  Google Scholar 

  9. Hayes, J. P., “Testing Logic Circuits by Transition Counting,” FTC-5, Digest of Papers, 1975 Symposium of Fault Tolerant Computing, Paris, France, June 1975, pp. 215–219.

    Google Scholar 

  10. Healy, J. T., “Economic Realities of Testing Microprocessors,” Digest of Papers, 1977 Semiconductor Test Symp., Oct. 1977, pp. 47–52.

    Google Scholar 

  11. Lee, E. C., “A Simple Concept in Microprocessor Testing,” Digest of Papers, 1976 Semiconductor Test Symp., Oct. 1976, 76CH1179–1C, pp. 13–15.

    Google Scholar 

  12. Losq, J., “Referenceless Random Testing,” FTCS-6, Digest of Papers, Sixth Int’l Symp. on Fault-Tolerant Computing, Pittsburgh, Penn., June 21–23, 1976, pp. 81–86.

    Google Scholar 

  13. Palmquist, S., and D. Chapman, “Expanding the Boundaries of LSI Testing with an Advanced Pattern Controller,” Digest of Papers, 1976 Semiconductor Test Symp., Oct. 1976, pp. 70–75.

    Google Scholar 

  14. Parker, K. P., “Compact Testing: Testing with Compressed Data,” FTCS-6, Digest of Papers, Sixth Int’l. Symp. on Fault-Tolerant Computing, Pittsburgh, Penn., June 21–23, 1976.

    Google Scholar 

  15. Shedletsky, J. J., “A Rationale for the Random Testing of Combinational Digital Circuits,” Digest of Papers, Compcon 75 Fall, Washington, D.C., Sept. 9–11, 1975, pp. 5–9.

    Google Scholar 

  16. Strini, V. P., “Fault Location in a Semiconductor Random Access Memory Unit,” IEEE-TC, Vol. C-27, No. 4, April 1978, pp. 379–385.

    Google Scholar 

  17. Weiler, C. W., “An Engineering Approach to IC Test System Maintenance,” Digest of Papers, 1977 Semiconductor Test Symp., Oct. 1977, pp. 144–145.

    Google Scholar 

References on Testability Measures

  1. Dejka, W. J., “Measure of Testability in Device and System Design,” Proc. 20th Midwest Symp. Circuits Syst., Aug. 1977, pp. 39–52.

    Google Scholar 

  2. Goldstein, L. H., “Controllability/Observability Analysis of Digital Circuits,” IEEE Trans. Circuits Syst., Vol. CAS-26, No. 9, Sept. 1979, pp. 685–693.

    Article  Google Scholar 

  3. Keiner, W. L., and R. P. West, “Testability Measures,” presented at AUTOTESTCON ’77, Nov. 1977.

    Google Scholar 

  4. Kovijanic, P. G., “Testability Analysis,” Digest of Papers, 1979 Test Conference, Oct. 1979, 79CH1509–9C, pp. 310–316.

    Google Scholar 

  5. Stephenson, J. E., and J. Grason, “A Testability Measure for Register Transfer Level Digital Circuits,” Proc. 6th Fault Tolerant Computing Symp., June 1976, pp. 101–107.

    Google Scholar 

References on Test Generation

  1. Agrawal, V., and P. Agrawal, “An Automatic Test Generation System for ILLIAC IV Logic Boards,” IEEE-TC, Vol. C-21, No. 9, Sept. 1972, pp. 1015–1017.

    Google Scholar 

  2. Armstrong, D. B., “On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Nets,” IEEE-TC, EC-15, Vol. 13, No. 2, Feb. 1966, pp. 63–73.

    Google Scholar 

  3. Betancourt, R. “Derivation of Minimum Test Sets for Unate Logical Circuits,” IEEE-TC, Vol. C-20, No. 11, Nov. 1973, pp. 1264–1269.

    MathSciNet  Google Scholar 

  4. Bossen, D. C., and S. J. Hong, “Cause and Effect Analysis for Multiple Fault Detection in Combinational Networks,” IEEE-TC, Vol. C-20, No. 11, Nov. 1971, pp. 1252–1257.

    Google Scholar 

  5. Bottorff, P. S., et al, “Test Generation for Large Networks,” Proc. 14th Design Automation Conf., June 1977, 77CH1216–1C, pp. 479–485.

    Google Scholar 

  6. Edlred, R. D., “Test Routines Based on Symbolic Logic Statements,” JACM, Vol. 6, No. 1, 1959, pp. 33–36.

    Article  Google Scholar 

  7. Hsieh, E. P., et al., “Delay Test Generation,” Proc. 14th Design Automation Conf., June 1977, 77CH1216–1C, pp. 486–491.

    Google Scholar 

  8. Ku, C. T., and G. M. Masson, “The Boolean Difference and Multiple Fault Analysis,” IEEE-TC, Vol. C-24, No. 7, July 1975, pp. 691–695.

    MathSciNet  Google Scholar 

  9. Muehldorf, E. I., “Test Pattern Generation as a Part of the Total Design Process,” LSI and Boards: Digest of Papers, 1978 Annual Semiconductor Test Symp., Oct. 1978, pp. 4–7.

    Google Scholar 

  10. Muehldorf, E. I., and T. W. Williams, “Optimized Stuck Fault Test Patterns for PLA Macros,” Digest of Papers, 1977 Semiconductor Test Symp., Oct. 1977, 77CH1216–7C, pp. 89–101.

    Google Scholar 

  11. Page, M. R., “Generation of Diagnositc Tests Using Prime Implicants,” Coordinated Science Lab Report R-414, University of Illinois, Urbana, Il., May 1969.

    Google Scholar 

  12. Papaioannou, S. G., “Optimal Test Generation in Combinational Networks by Pseudo Boolean Programming,” IEEE-TC, Vol. C-26, No. 6, June 1977, pp. 553–560.

    MathSciNet  Google Scholar 

  13. Parker, K. P., “Adaptive Random Test Generation,” Journal of Design Automation and Fault Tolerant Computing, Vol. 1, No. 1, Oct. 1976, pp. 62–83.

    Google Scholar 

  14. Parker, K. P., “Probabilistic Test Generation,” Technical Note No. 18, Jan. 1973, Digital Systems Laboratory, Stanford University, Stanford, Calif.

    Google Scholar 

  15. Poage, J. F., and E. J. McCluskey, “Derivation of Optimum Tests for Sequential Machines,” Proc. Fifth Annual Symp. on Switching Circuit Theory and Logic Design, 1964, pp. 95–110.

    Google Scholar 

  16. Poage, J. F., and E. J. McCluskey, “Derivation of Optimum Tests to Detect Faults in Combinational Circuits,” Mathematical Theory of Automation, Polytechnic Press, New York, 1963.

    Google Scholar 

  17. Putzolu, G. R., and J. P. Roth, “A Heuristic Algorithm for Testing of Asynchronous Circuits,” IEEE-TC, Vol. C-20, No. 6, June 1971, pp. 639–647.

    Google Scholar 

  18. Roth, J. P., W. G. Bouricius, and P. R. Schneider, “Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits,” IEEE-TEC, EC-16, Oct. 1967, pp. 567–580.

    MathSciNet  Google Scholar 

  19. Roth, J. P., “Diagnosis of Automata Failures: A Calculus and a Method,” IBM Journal of Research and Development, No. 10, Oct. 1966, pp. 278–281.

    Article  MATH  Google Scholar 

  20. Schneider, P. R., “On the Necessity to Examine D-chains in Diagnostic Test Generation-an Example,” IBM Journal of Research and Development, No. 11, Nov. 1967, p. 114.

    Article  Google Scholar 

  21. Schnurmann, H. D., E. Lindbloom, R. G. Carpenter, “The Weighted Random Test Pattern Generation,” IEEE-TC, Vol. C-24, No. 7, July 1975, pp. 695–700.

    Google Scholar 

  22. Sellers, E. F., M. Y. Hsiao, L. W. Bearnson, “Analyzing Errors with the Boolean Difference,” IEEE-TC, Vol. C-17, No. 7, July 1968, pp. 676–683.

    Google Scholar 

  23. Wang, D. T., “An Algorithm for the Detection of Test Sets for Combinational Logic Networks,” IEEE-TC, Vol. C-25, No. 7, July 1975, pp. 742–746.

    Google Scholar 

  24. Williams, T. W., and E. E. Eichelberger, “Ransom Patterns within a Structured Sequential Logic Design,” Digest of Papers, 1977 Semiconductor Test Symposium, Oct. 1977, 77CH1261–7C, pp. 19–27.

    Google Scholar 

  25. Yau, S. S., and S. C. Yang, “Multiple Fault Detection for Combinational Logic Circuits, IEEE-TC, Vol. C-24, No. 5, May 1975, pp. 233–242.

    MathSciNet  Google Scholar 

References on Simulation

  1. Armstrong, D. B., “A Deductive Method for Simulating Faults in Logic Circuits,” IEEE-TC, Vol. C-22, No. 5, May 1972, pp. 464–471.

    Google Scholar 

  2. Breuer, M. A., “Functional Partitioning and Simulation of Digital Circuits,” IEEE-TC, Vol. C-19, No. 11, Nov. 1970, pp. 1038–1046.

    Google Scholar 

  3. Chiang, H. Y. P., et al, “Comparison of Parallel and Deductive Fault Simulation,” IEEE-TC, Vol. C-23, No. 11, Nov. 1974, pp. 1132–1138.

    Google Scholar 

  4. Eichelberger, E. B., “Hazard Detection in Combinational and Sequential Switching Circuits,” IBM Journal of Research & Development, March 1965.

    Google Scholar 

  5. Manning, E., and H. Y. Chang, “Functional Technique for Efficient Digital Fault Simulation” IEEE Internat. Conv. Digest, 1968, p. 194.

    Google Scholar 

  6. Parker, K. P., “Software Simulator Speeds Digital Board Test Generation,” Hewlett Packard Journal, March 1979, pp. 13–19.

    Google Scholar 

  7. Seshu, S., “On an Improved Diagnosis Program,” IEEE-TEC, Vol. EC-12, No. 2, Feb. 1965, pp. 76–79.

    Google Scholar 

  8. Seshu, S., and D. N. Freeman, “The Diagnosis of Asynchronous Sequential Switching Systems,” IRE Trans, Elec. Comp., Vol. EC-11, No. 8, Aug. 1962, pp. 459–465.

    Article  MathSciNet  Google Scholar 

  9. Storey, T. M., and J. W. Barry, “Delay Test Simulation,” Proc. 14th Design Automation Conf., June 1977, 77CH1216–1C, pp. 491–494.

    Google Scholar 

  10. Szygenda, S. A., and E. W. Thompson, “Modeling and Digital Simulation for Design Verification Diagnosis,” IEEE-TC, Vol. C-25, No. 12, Dec. 1976, pp. 1242–1253.

    Google Scholar 

  11. Szygenda, S. A., “TEGAS2-Anatomy of a General Purpose Test Generation and Simulation System for Digital Logic,” Proc. 9th Design Automation Workshop, 1972, pp. 116–127.

    Google Scholar 

  12. Szygenda, S. A., D. M. Rouse, and E. W. Thompson, “A Model for Implementation of a Universal Time Delay Simulation for Large Digital Networks,” AFIPS Conf. Proc., Vol. 36, 1970, SJCC, pp. 207–216.

    Google Scholar 

  13. Ulrich, E. G., and T. Baker, “Concurrent Simulation of Nearly Identical Digital Networks,” Computer, Vol. 7, No. 4, April 1974, pp. 39–44.

    Google Scholar 

  14. Ulrich, E. G., and T. Baker, “The Concurrent Simulation of Nearly Identical Digital Networks,” Proc. 10th Design Automation Workshop, June 1973, pp. 145–150.

    Google Scholar 

  15. Ulrich, E. G., T. Baker, L. R. Williams, “Fault Test Analysis Techniques Based on Simulation,” Proc. 9th Design Automation Workshop, 1972, pp. 111–115.

    Google Scholar 

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© 1984 Martinus Nijhoff Publishers, Dordrecht

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Williams, T.W. (1984). Design for Testability. In: Antognetti, P., Pederson, D.O., de Man, H. (eds) Computer Design Aids for VLSI Circuits. NATO ASI Series, vol 48. Springer, Dordrecht. https://doi.org/10.1007/978-94-011-8006-1_8

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