Mathematical Models for the VLSI Planarization Problem

Abstract

The temptation of creating a general-purpose graph model for a circuit adequate to the planarization problem has already long been experienced by the designers of CAD systems. This would allow us to apply the efficient graph algorithms of Chapter 2 for at least circuit planarity testing. It is interesting to note that investigations in this direction had been started well before the highly efficient Hopcroft-Tarjan, Rubin algorithm and other were reported. However, numerous investigations revealed that such a general purpose graph model does not exist in practice for an arbitrary electrical circuit. Moreover it has been ascertained that to planarize a wide class of circuits one must turn to hypergraph models.