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Analog and Mixed-Level Simulation with Implications to VHDL

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Fundamentals and Standards in Hardware Description Languages

Part of the book series: NATO ASI Series ((NSSE,volume 249))

Abstract

Analog simulation was first applied to the analysis of discrete circuits, but it rapidly evolved to handle integrated circuits (IC) as well. Analog simulation was used for a long time to verify the behavior of small to medium-size electrical circuits (up to a few hundreds of transistors). However, due to the growing complexity of ICs, it became necessary to develop new analysis techniques capable of handling huge amounts of data efficiently and of allowing more abstract models for the circuit components. Typically, not all parts of an electrical circuit need to be simulated at the same level or at the same accuracy during the same run. Mixed-level simulation allows one to describe parts of the circuit at different levels of details and to simulate them accordingly, while mixed-mode simulation uses digital and analog simulation techniques simultaneously. VHDL is now gaining a lot of popularity as a powerful way to model, simulate, and synthesise digital hardware. Analog extensions to VHDL are currently under study and they have to take into account analog and mixed-level/mixed-mode simulation techniques.

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Author information

Authors and Affiliations

  1. Integrated Circuit Design Center (LEG/C3i), Swiss Federal Institute of Technology (EPFL), CH-1015, Lausanne, Switzerland

    Alain Vachoux

  2. Object Design, Inc., Burlington, MA, 01803, USA

    Kevin Nolan

Authors
  1. Alain Vachoux
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  2. Kevin Nolan
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Editors and Affiliations

  1. Laboratoire ARTEMIS, Université Joseph Fourier, Grenoble, France

    Jean P. Mermet (Directeur de Recherche au CNRS) (Directeur de Recherche au CNRS)

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Vachoux, A., Nolan, K. (1993). Analog and Mixed-Level Simulation with Implications to VHDL. In: Mermet, J.P. (eds) Fundamentals and Standards in Hardware Description Languages. NATO ASI Series, vol 249. Springer, Dordrecht. https://doi.org/10.1007/978-94-011-1914-6_9

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  • DOI: https://doi.org/10.1007/978-94-011-1914-6_9

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