Formal proofs from HDL descriptions

Abstract

In order to achieve bug-free designs, two complementary strategies have been actively developed: Automatic synthesis generates under specified constraints, from a behavioural description of a circuit, a layout of interconnected components such that the resulting network produces the same behaviour and satisfies the constraints; such designs are functionally correct by construction if the primitive components have been fully verified, and if the transformations used to map behavioural statements into a network of primitive components are themselves correct. However, to check the result of the synthesis software (which in general has not been proven bug-free), and in the case of manual or humanassisted design, a thorough verification of the design functional correctness has to be performed. Except for very small circuits, the functional verification by exhaustive simulation is impractical. This is why, for the last ten years, considerable research efforts have gone into finding theoretical models, proof methods and efficient algorithms to perform the formal verification of a design correctness. Correctness is not an absolute concept, but rather relates to several quite distinct attributes, such as checking desired timing characteristics (set-up, hold time,...), properties ( safety, liveness, etc.), or functional behaviour. In this paper, we shall concentrate on the last two aspects, and shall consider the following partial definition: formally verifying a circuit design consists in proving that, for all acceptable initial state values and for all possible input values, the design implementation (how it is built) realizes its specification (its expected behavior). Results obtained in the last years show that such verifications are applicable to reasonably complex circuits.