Abstract
The advent of hardware description languages such as VHDL allows one to create behavioral models which accurately represent the functionality and timing of complex devices. However the coding and testing of complicated behavioral models is labor intensive and error prone. In this chapter we describe a system which can significantly speed up the development of error free models. Also, as the model is developed, tests which thoroughly exercise the model can be generated automatically.
Work described in this chapter was supported in part by the National Science Foundation under grant No. MIP 9120620, SRC under grant 91-DJ-230, and CIT under grant INF-92-00S.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Armstrong, J. R., Chip-Level Modeling with VHDL, Prentice Hall Inc. August 1988.
Lipsett, R. et al., Hardware Description and Design, Kluwer Academic Publishers, 1989.
Coelho, D., The VHDL Handbook, Kluwer Academic Publishers, 1989.
Steven S. Leung, et. al., ASIC System Design with VHDL: A Paradigm, Kluwer Academic Publishers, 1989.
Perry, D., VHDL, McGraw-Hill, 1991.
Mazor, S. and Langstraat, P., A Guide to VHDL, Kluwer Academic Publishers, 1992.
IEEE Standard VHDL Language Reference Manual, 1988
F. Vahid, S. Narayan, D.D. Gajski, “Spec Charts: A Language for System Level Synthesis,” Proceeding of CHDL-91, pp. 165–174 , April 1991.
A. Gadagkar and J.R. Armstrong, “Timing Distribution in VHDL Behavioral Models,” Proceedings of ICCAD’92.
Barclay, D.S. and Armstrong, J.R., “A Heuristic Chip-Level Test Generation Algorithm,” Proceedings of the 23rd Design Automation Conference, June 1986, pp. 257–262.
Cho C.H., and Armstrong J.R., “ VHDL Semantics for Behavioral Test Generation”. Proceeding of CHDL-91, pp. 395–412 , April 1991.
Hummer, H.D., Veit, H., and Topfer, H., “Functional Tests for Hardware Described from VHDL”, Proceedings of CHDL-91,pp. 465–477, April 1991.
Levendel, Y. H. and Menon, P. R., “Test Generation Algorithms for Computer Hardware Description Languages”, IEEE Trans. Computers, vol c-31, pp.577–588, July 1982.
O’Neil, M.D.,Jani, D.D.,Cho C.H., and Armstrong, J.R.,“BTG: A Behavioral Test Generator”, Proceedings of CHDL-89, pp 347–361.
Murray, B.T.; Hayes, J.P., “Hierarchical Test Generation Using Precomputed Tests for Modules”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.9, No.6, pp.594–603, June 1990.
P.C. Ward and J.R. Armstrong, “Behavioral Fault Simulation in VHDL”, Proceedings of the 27th Design Automation Conference, June 1990, pp 587–593.
Myers, G. J., The Art of Software Testing, John Wiley and Sons, Inc., 1979.
Synopsys Inc., “VHDL System Simulator Reference Manual”, November 1990.
Genrad Incorporated, “System HILO HIFAULT Reference Manual”
Genrad Incorporated,“System HILO GHDL Reference Manual”
Genrad Incorporated,“System HILO DWL Reference Manual”
Synopsys Inc., “Design Compiler Reference Manual”
J.R.Armstong and F.G.Gray, “Structured Logic Design with VHDL”, Prentice Hall, March 1993 (to appear)
C. Chao and F.G.Gray, “Microoperation Perturbations in Chip Level Fault Modeling”, 25th Design Automation Conference, pp. 579–582, June 1988
C. H. Cho and J.R. Armstrong, “Heuristic Test Generation For Chip Level Circuit Descriptions,” IEEE VLSI Test Workshop, 1988
W. Cyre, “Mapping Design Knowledge from Multiple Representations”, Proc. 1991 IEEE Conference on Computer Design, Boston, MA, Oct. 1991.
Sanat R. Rao, Biyu Pan, and J.R. Armstrong, Hierarchical Test Generation for VHDL Behavioral Models, Proceedings of the European Design Automation Conference, February 1993.
M. Manek, W. R. Cyre, and J.R. Armstrong, Natural Language Interface to a VHDL Modeling Tool, submitted to ICCD-93.
A. J. Honcharik, J. R. Armstrong, and W. R. Cyre, “Generation of VHDL Models from Informal Specifications”, submitted to ICCAD-93.
Gunjeet Baweja and J.R.Armstrong, Gate Level Coverage of a Behavioral Test Generator, submitted to ITC 83.
C. Chao and F.G. Gray, “Microoperation Peturbation in Chip Level Fault Modeling,” 25th Design Automation Conference, pp. 579–582, June 1988.
B.Singh, J.Wicks, P.Wright, J.R.Armstrong, “The Modeler’s Assistant: A CAD Tool for Behavioral Model Development”, Proceedings of CHDL’93, pp. 347–354, April 1993.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1993 Springer Science+Business Media Dordrecht
About this chapter
Cite this chapter
Armstrong, J.R., Honcharik, A. (1993). Rapid Development and Testing of Behavioral Models. In: Mermet, J.P. (eds) Fundamentals and Standards in Hardware Description Languages. NATO ASI Series, vol 249. Springer, Dordrecht. https://doi.org/10.1007/978-94-011-1914-6_10
Download citation
DOI: https://doi.org/10.1007/978-94-011-1914-6_10
Publisher Name: Springer, Dordrecht
Print ISBN: 978-94-010-4846-0
Online ISBN: 978-94-011-1914-6
eBook Packages: Springer Book Archive