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Hierarchical, Parallel and Systolic Array Processing

  • Chapter
The Impact of Processing Techniques on Communications

Part of the book series: NATO ASI Series ((NSSE,volume 91))

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Abstract

Many signal processing algorithms are highly regular, data-independent, and access the data in fixed patterns. For these reasons the current technological advances in very large scale integrated circuits hold especially great promise for signal processing, and in fact we now see the development of many highly integrated processors of a more or less specialized nature. At one end of the spectrum, we see programmable signal processing chips that are really microprocessors, with program, memory and logic separated as in a general purpose machine. At the other extreme, we see highly-specialized, custom chips that perform fixed tasks; typically the data moves through the chip along fixed, regular paths, the arithmetic logic is distributed in space, and the “program” is really “hard-wired” into the topology. This talk is devoted to a study of this latter, custom variety of architecture.

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Author information

Authors and Affiliations

  1. Electrical Engineering and Computer Science Department, Princeton University, Princeton, New Jersey, 08544, USA

    Kenneth Steiglitz

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  1. Kenneth Steiglitz
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Editor information

Editors and Affiliations

  1. Marconi Research Centre, GEC Research Laboratories, Great Baddow, Essex, UK

    J. K. Skwirzynski

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© 1985 Martinus Nijhoff Publishers, Dordrecht

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Steiglitz, K. (1985). Hierarchical, Parallel and Systolic Array Processing. In: Skwirzynski, J.K. (eds) The Impact of Processing Techniques on Communications. NATO ASI Series, vol 91. Springer, Dordrecht. https://doi.org/10.1007/978-94-009-5113-6_5

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  • DOI: https://doi.org/10.1007/978-94-009-5113-6_5

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-94-010-8760-5

  • Online ISBN: 978-94-009-5113-6

  • eBook Packages: Springer Book Archive

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