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Testing and Diagnosis of VLSI and ULSI pp 355–381Cite as

Testing of Processing Arrays

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Part of the book series: NATO ASI Series ((NSSE,volume 151))

Abstract

Processing arrays have been in recent years the subject of many research activities, with particular reference to their implementation by means of VLSI or WSI devices; in fact, while their regular structure, characterized by high locality of interconnections, makes them well suited to high integration, relevant speed performances and the possibility of mapping upon them advanced signal-processing algorithms creates an obvious interest for such demanding applications as real-time radar imaging (and, more in general, signal processing) etc.

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Reference

  1. E.M. Aboulhamid, E. Cerny:”Built-in Testing of One-Dimensional Unilateral Iterative Arrays”, IEEE Trans. on Computers, Vol. C33, pp. 560 – 564, June 1984

    Article  Google Scholar 

  2. H A.Anderson:”Computer-aided design and testing for RVLSI”, International Workshop on WSI, Southampton, 1985

    Google Scholar 

  3. M. Annaratone, R.Stefanelli:”A multiplier with multiple error correction capabilities”, Proc. 6th Symposium on Computer Arithmetics, 1983

    Google Scholar 

  4. A.Chatterjee, J.A.Abraham:“ C-Testability for generalized tree structures with applications to Wallace Trees and other circuits”, ICCAD-86 pp 288–291

    Google Scholar 

  5. Y.W.Choi, S.H.Han, M.Malek:“Fault diagnosis of reconfigurable systolic arrays“, ICCD-84, 451–455

    Google Scholar 

  6. Y.H.Choi, D.S.Fussell, M.Malek:”Token-triggered systolic diagnosis of Wafer-scale arrays”, Int’l workshop on WSI, Southampton, 1985

    Google Scholar 

  7. Y.H.Choi, D.S.Fussell, M.Malek:“Fault diagnosis of switches in Wafer-Scale arrays“, ICCAD-86, 292–297

    Google Scholar 

  8. F.J.O. Dias:”Truth-table verification of an iterative logic array“, IEEE Trans, on Computer, vol. C25, pp. 605 – 613, June 1976

    Article  MathSciNet  Google Scholar 

  9. F. Distante, M.G. Sami, R. Stefanelli:”Testing techniques for Complex VLSI/WSI Processing Arrays” S. Kartashev, S. Kartashev eds., Van Nostrand Reinhold Publisher

    Google Scholar 

  10. H. Elhuni, A. Vergis, L. Kinney:”C-testability of two-dimensional arrays of combinatorial cells”, Proc. ICC AD 85 pp. 74–76

    Google Scholar 

  11. R.A.Evans, J.V.McCanny, K.W.Wood:”Wafer scale integration based on self organization”, Int’l Wowkshop on WSI, Southampton, 1985

    Google Scholar 

  12. R.Evans, J.McWhirter:” A testing strategy for self-organising fault-tolerant arrays”, Oxford Workshop on systolic arrays, Oxford, July 1986

    Google Scholar 

  13. A.D. Friedman, P.R. Menon:”Fault detection in Digital Circuits”, Englewood Cliffs, NJ: Prentice-Hall, 1971

    Google Scholar 

  14. A.D. Friedman:”Easily testable iterative systems”, IEEE Trans, on Computer, vol. C22, pp. 1061 – 1064, Dec 1973

    Article  Google Scholar 

  15. S.L. Hakimi, A.T. Amin:”Characterization of connection assignment of diagnosable systems”, IEEE Trans Computers, Vol. C-23, pp 86 – 88, Jan 1974

    Google Scholar 

  16. W.H. Kautz:”Testing for faults in combinatorial cellular logic arrays”, Proc. 8th Symp. Switching Automata Theory, 1967, pp. 161 – 174

    Google Scholar 

  17. T.Mangir:”Sources of failures andyield imporvement for VLSI and restructurable interconnect for R-VLSI and WSI:

    Google Scholar 

  18. Sources of failure and yield improvement for VLSI”, Proc. IEEE, June 1984, 690 – 708

    Google Scholar 

  19. Restructurable interconnects for RVLSI and WSI”, Proc IEEE, Dec 1984, 1687 – 1694.

    Google Scholar 

  20. R. Parthasarathy, S.M. Reddy:”A Testable design for Iterative Logic”, IEEE Trans. on Computer, Vol. C30, pp. 883 – 841, 1981

    MathSciNet  Google Scholar 

  21. S.Laha, J.H.Patel:”Error correction in arithmetic operations using time redundancy”, FTCS-13, 298–305

    Google Scholar 

  22. F.P.Preparata, G.Metze, R.T.Chien:”On the connection assignment problem of diagnosable systems”, IEEE Trans. Electronic Computers, Vol. EC-16, N. 6, Dec 1967, p. 848

    Article  Google Scholar 

  23. M.G.Sami, R.Stefanelli:” Self-testing array structures”, ICCD-84, pp. 677–682

    Google Scholar 

  24. L. Snyder:”Introduction to the configurable highly parallel computer”, IEEE Computer Magazine, vol. 15, n. 1, Jan 82, pp 47–56

    Google Scholar 

  25. J.T.Scanlon,W.K.Fuchs:”A testing strategy for bit-serial arrays”, ICCAD-86, pp. 284–287

    Google Scholar 

  26. T. Sridhar, J.P. Hayes:”Testing bit-sliced Microprocessors”, Proc. FTCS 9, 1979, pp. 211 – 218

    Google Scholar 

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Author information

Authors and Affiliations

  1. Department of Electronics, Politecnico di Milano, Italy

    F. Distante, M. G. Sami & R. Stefanelli

Authors
  1. F. Distante
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  2. M. G. Sami
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  3. R. Stefanelli
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Editor information

Editors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Colorado at Boulder, Boulder, Colorado, USA

    Fabrizio Lombardi

  2. Department of Computer Science, Texas A&M University, College Station, Texas, USA

    Fabrizio Lombardi

  3. Dipartimento di Electtronica, Politecnico di Milano, Milano, Italy

    Mariagiovanna Sami

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© 1988 Kluwer Academic Publisher

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Distante, F., Sami, M.G., Stefanelli, R. (1988). Testing of Processing Arrays. In: Lombardi, F., Sami, M. (eds) Testing and Diagnosis of VLSI and ULSI. NATO ASI Series, vol 151. Springer, Dordrecht. https://doi.org/10.1007/978-94-009-1417-9_15

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  • DOI: https://doi.org/10.1007/978-94-009-1417-9_15

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-94-010-7134-5

  • Online ISBN: 978-94-009-1417-9

  • eBook Packages: Springer Book Archive

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