Performance and Physical Limits of Heterostructure Field Effect Transistors

Abstract

The technological progress made in the first 9 months of this ESPRIT basic research action is reviewed. The primary goal of this project over a 2.5 year period is the study of the physical limits of carrier transit time and hence device switching speed as heterojunction field effect transistors (HFETs) are scaled down from submicron to ultra submicron dimensions (0.2–0.02μm gate length). Since the switching time of heterostructure field effect transistors only approach the carrier transit time when the device parasitics are minimized, an analysis of various techniques to reduce gate resistance for sub-100nm gate lengths is made including the consideration of superconducting gate electrodes. The most promising approach is the use of multi-fingered gates or multiple gate feeds with a normally conducting gate metal, combined with gate aspect ratios as large as is practical to fabricate. Nanometer scale structures have been fabricated on bulk substrates with PMMA liftoff, and contamination resist and ion milling down to 16nm. A 35nm by 25μm gate electrode has been fabricated in 0.4μm source drain gap of a device structure, and at L2M a 0.15μm gate length AlGaAs/GaAs HFET with transconductance of 694mS/mm and f_max of 132GHz has been achieved. Working pseudomorphic AlGaAs/InGaAs HFETs with InAs grown ohmic contacts and nanometer scale gate electrodes are expected in the next trimester.