Bachus: A VLSI Architecture for a Large Binary Associative Memory

Abstract

In recent years many attempts have been made to realise neural networks using VLSI technology. Thereby, major difficulties are how to implement several hundreds or, if possible, thousands of highly interconnected neurons with their synapses on the area of one chip or to develop cascadeable architectures. Due to the large number of conceivable architectures many, more or less convincing approaches have been made. Some of them are trying to take advantage of analog VLSI circuits, whereby one has to take into account many problems concerning parameters depending on fabrication and temperature. Other researchers developed wholly digital circuits, causing problems with chip area, synchronisation, and information exchange in highly interconnected networks. With this paper we want to present a digital implementation of a binary network using VLSI technology. Due to the lack of on-chip learning support and the use of industrial standard RAMs, we are able to offer an extremely dense storage of binary synaptic weights. Therefore, it is feasible to realise network structures with several thousand completely connected neurons. Such a network may be used for applications in the areas of speech and image recognition.