Programmable Chips In Consumer Electronics and Telecommunications

Architectures and Design Technology
  • G. Goossens
  • J. Van Praet
  • D. Lanneer
  • W. Geurts
  • F. Thoen
Part of the NATO ASI Series book series (NSSE, volume 310)

Abstract

Mobile and personal communication systems, and multi-media are among the most prominently growing sectors of the electronics industry today. As an illustration, Figure 1 gives an indication of the volume of some personal communication applications in the European market. New business and home applications are emerging, using advanced communication media such as satellite links, cellular radio, or high-speed optical networks. The success of these developments will however depend to a great extent on the ability to realise complex digital signal processing functionalities in cost-efficient VLSI chips.

Keywords

Data Path Register Allocation Embed Processor Very Long Instruction Word Machine Cycle 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    A.V. Aho and S.C. Johnson. Optimal code generation for expression trees. J. ACM, 23(3):488–501, July 1976.MathSciNetMATHCrossRefGoogle Scholar
  2. 2.
    A.V. Aho, R. Sethi, and J.D. Ullman. Compilers — principles, techniques, and tools. Addison-Wesley, Reading, 1986.Google Scholar
  3. 3.
    A.V. Aho, M. Ganapathi, and S.W.K. Tjiang. Code generation using tree matching and dynamic programming. ACM Trans. Prog. Lang, and Systems, 11(4):491–516, Oct. 1989.CrossRefGoogle Scholar
  4. 4.
    A. Alomary, T. Nakata, Y. Honma, M. Imai, and N. Hikichi. An ASIP instruction set optimization algorithm with functional module sharing constraints. In Proc. IEEE/ACM Int. Conf. Comp.-Aided Design, pp. 526–532, Santa Clara, Nov. 1993.Google Scholar
  5. 5.
    G. Araujo and S. Malik. Optimal code generation for embedded memory non- homogeneous register architectures. In Proc. IEEE/ACM Int. Symp. System Synthesis, Cannes, Sept. 1995.Google Scholar
  6. 6.
    P. Briggs, K.D. Cooper, and L. Torczon. Rematerialization. In Proc. ACM SIG- PLAN Conf. Prog. Lang. Design and Implement., pp. 311–321, 1992.Google Scholar
  7. 7.
    F. Catthoor and H. De Man. Application-specific architectural methodologies for high-throughput digital signal and image processing. IEEE Tr. Acoustics, Speech and Signal Processing, 38(2):339–349, Feb. 1990.CrossRefGoogle Scholar
  8. 8.
    G.J. Chaitin. Register allocation and spilling via graph coloring. In Proc. ACM SIGPLAN Conf. Progr. Lang. Design and Implement., pp. 98–105, 1982.Google Scholar
  9. 9.
    M. Chiodo, P. Giusto, A. Jurecska, H.C. Hsieh, A. Sangiovanni-Vincentelli, and L. Lavagno. Hardware-software co-design of embedded systems. IEEE Micro, 14(4), Aug. 1994.Google Scholar
  10. 10.
    P. Chou and G. Borriello, Software scheduling in the co-design of reactive real-time systems. In Proc. 31st ACM/IEEE Design Autom. Conf., San Diego, June 1994.Google Scholar
  11. 11.
    M. Cornero, F. Thoen, G. Goossens, and F. Curatelli. Software synthesis for realtime information processing systems. In Code generation for embedded processors, pp. 260–279, Kluwer Acad. Publ., Boston, 1995.Google Scholar
  12. 12.
    R. Cytron, J. Ferrante, B. Rosen, M. Wegman, and K. Zadeck. Efficiently computing static single assignment form and the control dependence graph. ACM Trans. Prog. Lang, and Systems, 13(4):451–490, Oct. 1991.CrossRefGoogle Scholar
  13. 13.
    S. Davidson, D. Landskov, B.D. Shriver, and P.W. Mallett. Some experiments in local microcode compaction for horizontal machines. IEEE Tr. Comp., C-30 (7): 460–477, July 1981.CrossRefGoogle Scholar
  14. 14.
    J.W. Davidson and C.W. Fraser. Code selection through object code optimization. ACM Trans. Prog. Lang, and Systems, 6(4):505–526, Oct. 1984.CrossRefGoogle Scholar
  15. 15.
    H. De Man, F. Catthoor, G. Goossens, J. Vanhoof, J. Van Meerbergen, S. Note, and J. Huisken. Architecture driven synthesis techniques for VLSI implementation of DSP algorithms. Proc. of the IEEE, 78(2):319–336, Feb. 1990.CrossRefGoogle Scholar
  16. 16.
    H. De Man, I. Bolsens, B. Lin, K. Van Rompaey, S. Vercauteren, and D. Verkest. Co-design of DSP systems. NATO ASI Hardware/Software Co-Design, Tremezzo, June 1995.Google Scholar
  17. 17.
    DSP Architect — DEL — User’s and Reference Manual. Mentor Graphics Corp./E.D.C., Leuven, 1993.Google Scholar
  18. 18.
    J.R. Ellis. BULLDOG: a compiler for VLIW architectures. MIT Press, Cambridge, 1986.Google Scholar
  19. 19.
    G. Essink, E. Aarts, R. van Dongen, P. van Gerwen, J. Korst, and K. Vissers. Architecture and programming of a VLIW style programmable video signal processor. In Proc. 24th ACM/IEEE Intl. Symp. on Microarchitecture, pp. 181–188, Albuquerque, Nov. 1991.Google Scholar
  20. 20.
    A. Fauth, G. Hommel, C. Müller, and A. Knoll. Global code selection for directed acyclic graphs. In Proc. ACM Int. Conf. Compiler Construction, pp. 128–142, Edinburgh, April 1994.Google Scholar
  21. 21.
    A. Fauth, J. Van Praet, and M. Freericks. Describing instruction set processors using nML. In Proc. Europ. Design and Test Conf., Paris, March 1995.Google Scholar
  22. 22.
    A. Fauth. Beyond tool-specific machine description languages. In Code generation for embedded processors, pp. 138–152, Kluwer Acad. Publ., Boston, 1995.Google Scholar
  23. 23.
    J.A. Fisher. Trace scheduling: a technique for global microcode compaction. IEEE Tr. Comp., C-30(7):478–490, July 1981.CrossRefGoogle Scholar
  24. 24.
    C.W. Fraser and R.R. Henry. BURG — Fast optimal instruction selection and tree parsing. ACM Sigplan Notices, 27(4):68–76, April 1992.CrossRefGoogle Scholar
  25. 25.
    M. Freericks. The nML machine description formalism. Technical Report, T.U. Berlin, 1992.Google Scholar
  26. 26.
    M. Ganapathi, C.N. Fisher, and J.L. Hennessy. Retarget able compiler code generation. Computing Surveys, 14(4):573–593, 1982.CrossRefGoogle Scholar
  27. 27.
    K. Ghosh, B. Mukherjee, and K. Schwan. A survey of real-time operating systems. Technical Report, Georgia Inst, of Technology, Atlanta, Feb. 1994.Google Scholar
  28. 28.
    G. Goossens, F. Catthoor, D. Lanneer, and H. De Man. Integration of signal processing systems on heterogeneous IC architectures. In Proc. 6th ACM/IEEE Intl. Workshop High Level Synthesis, Dana Point, Nov. 1992.Google Scholar
  29. 29.
    G. Goossens, I. Bolsens, B. Lin, and F. Catthoor. Design of heterogeneous ICs for mobile and personal communication systems. In Proc. IEEE Intl. Conf. Comp.-Aided Design, pp. 524–531, San Jose, Nov. 1994.Google Scholar
  30. 30.
    G. Goossens, D. Lanneer, M. Pauwels, F. Depuydt, K. Schoofs, A. Kifli, M. Cornero, P. Petroni, F. Catthoor, and H. De Man. Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures. J. VLSI Signal Processing, 9(l):49–65, 1995.CrossRefGoogle Scholar
  31. 31.
    R.K. Gupta. Co-synthesis of hardware and software for digital embedded systems. Ph.D Dissertation, Stanford Univ., Dec. 1993.Google Scholar
  32. 32.
    R. Hartmann. Combined scheduling and data routing for programmable ASIC systems. In Proc. Europ, Conf. Design Autom., pp. 486–490, Brussels, March 1992.Google Scholar
  33. 33.
    J.L. Hennessy and D.A. Patterson. Computer architecture: a quantitative approach. Morgan Kaufmann Publishers Inc., San Mateo, 1990.Google Scholar
  34. 34.
    B.C. Holmer and A.M. Despain. Viewing instruction set design as an optimization problem. In Proc. 24th ACM/IEEE Int. Symp. Microarch., pp. 153–162, Albuquerque, Nov. 1991.Google Scholar
  35. 35.
    I.-J. Huang and A.M. Despain. Generating instruction sets and microarchitectures from applications. In Proc. IEEE/ACM Int. Conf. Comp.-Aided Design, pp. 391–396, San Jose, Nov. 1994.Google Scholar
  36. 36.
    G. Kane. MIPS RISC architecture. Prentice-Hall, 1989.Google Scholar
  37. 37.
    M. Lam. Software pipelining: an effective scheduling technique for VLIW machines. In Proc. ACM SIGPLAN Conf. Prog. Lang. Design and Implement., pp. 318–328, Atlanta, 1988.Google Scholar
  38. 38.
    D. Landskov, S. Davidson, B. Shriver, and P. Mallett. Local microcode compaction techniques. ACM Comput. Surveys, 12(3):261–294, Sept. 1980.CrossRefGoogle Scholar
  39. 39.
    D. Lanneer, M. Cornero, G. Goossens, and H. De Man. Data routing: a paradigm for efficient data-path synthesis and code generation. In Proc. 7th ACM/IEEE Int. Symp. on High-Level Synthesis, pp. 17–22, Niagara-on-the-Lake, May 1994.Google Scholar
  40. 40.
    D. Lanneer, J. Van Praet, A. Kifli, K. Schoofs, W. Geurts, F. Thoen, and G. Goossens. CHESS: retargetable code generation for embedded DSP processors. In Code generation for embedded processors, pp. 85–102, Kluwer Acad. Publ., Boston, 1995.Google Scholar
  41. 41.
    E.A. Lee. Programmable DSP architectures: Part I Part II. IEEE ASSP Magazine. Dec. 1988 and Jan. 1989.Google Scholar
  42. 42.
    M.T-C. Lee, V. Tiwari, S. Malik, and M. Fujita. Power analysis and low-power scheduling techniques for embedded DSP software. In Proc. IEEE/ACM Int. Symp. System Synthesis, Cannes, Sept. 1995.Google Scholar
  43. 43.
    C. Liem, T. May, and P. Paulin. Instruction-set matching and selection for DSP and ASIP code generation. In Proc. Europ. Design and Test Conf., pp. 31–37, Paris, Feb. 1994.Google Scholar
  44. 44.
    C. Liem, T. May, and P. Paulin. Register assignment through resource classification for ASIP microcode generation. In Proc. ACM/IEEE Int. Conf. Comp.-Aided Design, pp. 397–402, San Jose, Nov. 1994.Google Scholar
  45. 45.
    P. Marwedel and G. Goossens (ed.). Code generation for embedded processors. Kluwer Acad. Publ., Boston, 1995.Google Scholar
  46. 46.
    M.C. McFarland. The Value Trace: a data base for automated digital design. Techn. Report, CMU, Pittsburgh, Dec. 1978.Google Scholar
  47. 47.
    M.C. McFarland, A.C. Parker, and R. Camposano. The high level synthesis of digital systems. Proc. of the IEEE, 78(2):301–318, Feb. 1990.CrossRefGoogle Scholar
  48. 48.
    L. Nowak and P. Marwedel. Verification of hardware descriptions by retargetable code generation. In Proc. 26th ACM/IEEE Design Autom. Conf., pp. 441–447, Las Vegas, June 1989.Google Scholar
  49. 49.
    OAK Architecture Specifications. DSP Semiconductor, Santa Clara, may 1994Google Scholar
  50. 50.
    P.G. Paulin, C. Liem, T.C. May, and S. Sutarwala. DSP design tool requirements for embedded systems : a telecommunications industrial perspecive. J. VLSI Signal Processing, 9(1), 1995.CrossRefGoogle Scholar
  51. 51.
    P.G. Paulin, C. Liem, T.C. May, and S. Sutarwala. FLEXWARE: a flexible firmware development environment for embedded system.In Code generation for embedded processors, pp. 67–84, Kluwer Acad. Publ., Boston, 1995.Google Scholar
  52. 52.
    PINE Architecture Specifications. DSP Semiconductors, Santa Clara, Sept. 1993.Google Scholar
  53. 53.
    J.F. Ready. VRTX: a real-time operating system for embedded microprocessor applications. IEEE Micro, 8–17, Aug. 1986.Google Scholar
  54. 54.
    K. Rimey and P.N. Hilfìnger. A compiler for application-specific signal processors. In VLSI Signal Processing III, pp. 341–351, IEEE Press, New York, 1988.Google Scholar
  55. 55.
    J. Sato, M. Imai, T. Hakata, A.Y. Alomary, and N. Hikichi. An integrated design environment for application-specific integrated processors. In Proc. IEEE Int. Conf. Comp. Design, pp. 414–417, Rochester, Oct. 1991.Google Scholar
  56. 56.
    Spox — the DSP operating system. Spectron Microsystems, Santa Barbara, 1992.Google Scholar
  57. 57.
    R.M. Stallman. Using and porting GNU CC. Free Software Foundation, June 1993.Google Scholar
  58. 58.
    V. Tiwari, S. Malik, and A. Wolfe. Power analysis of embedded software: a first step towards software power minimization. In Proc. IEEE Int. Conf. Comp.-Aided Design, pp. 384–390, San Jose, Nov. 1994.Google Scholar
  59. 59.
    J.T.J, van Eijndhoven and L. Stok. A data flow graph exchange standard. In Proc. Europ. Design Autom. Conf., pp. 193–199, Brussels, March 1992.Google Scholar
  60. 60.
    P. Vanoostende, E. Van Zieleghem, E. Rousseau, C. Massy, and F. Gérard. Retar- getable code generation: key issues for successful introduction. In Code generation for embedded processors, pp. 32–47, Kluwer Acad. Publ., Boston, 1995.Google Scholar
  61. 61.
    J. Van Praet, G. Goossens, D. Lanneer, and H. De Man. Instruction set definition and instruction selection for ASIPs. In Proc. 7th ACM/IEEE Int. Symp. High-Level Synthesis, pp. 11–16, Niagara-on-the-Lake, May 1994.Google Scholar
  62. 62.
    J. Van Praet, D. Lanneer, G. Goossens, W. Geurts, and H. De Man. A graph based processor model. Submitted for publication, 1995.Google Scholar
  63. 63.
    S.R. Vegdahl. Phase coupling and constant generation in an optimizing microcode compiler. In Proc. 15th Micro, pp. 125–133, 1982.Google Scholar
  64. 64.
    E. Verhulst. Virtuoso: providing sub-microsecond context switching on DSPs with a dedicated nano kernel. In Proc. Int. Conf. Signal Proc. Applications and Technology, Santa Clara, 1993.Google Scholar
  65. 65.
    D. Weinsziehr, G-H. Huamann-Bollo, G. Mahlich, J. Preißner, J. Schuck, H. Sahm, P. Weingart, and J. Yeandel. KISS-16V2: a one-chip ASIC DSP solution for GSM. In Proc. IEEE Custom Integr. Circ. Conf., pp. 10.4.1–10.4.4, 1992.Google Scholar
  66. 66.
    B. Wess. Code generation based on trellis diagrams. In Code generation for embedded processors, pp. 188–202, Kluwer Acad. Publ., Boston, 1995.Google Scholar
  67. 67.
    T. Wilson, G. Grewal, B. Halley, and D. Banerji. An integrated approach to retar- getable code generation. In Proc. 7th ACM/IEEE Int. Symp. High-Level Synthesis, pp. 70–75, Niagara-on-the-Lake, May 1994.Google Scholar
  68. 68.
    V. Živojnović, J. Martínez, C. Schläger, and H. Meyr. DSPstone : a DSP-Oriented Benchmarking methodology. In Pro. Int. Conft. Signal proc. Applications and Technology, Dallas, Oct. 1994.Google Scholar

Copyright information

© Kluwer Academic Publishers 1996

Authors and Affiliations

  • G. Goossens
    • 1
  • J. Van Praet
    • 1
  • D. Lanneer
    • 1
  • W. Geurts
    • 1
  • F. Thoen
    • 1
  1. 1.IMECLeuvenBelgium

Personalised recommendations