Advertisement

Techniques and Devices

  • Jacopo Franco
  • Ben Kaczer
  • Guido Groeseneken
Chapter
Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 47)

Abstract

In this Chapter, the measurement techniques and the devices used in this work are described. An overview of the state-of-the-art of relaxation-aware NBTI measurement techniques is given. The methodology used for assessing the device reliability from raw measurement data is discussed. The process flow of the studied (Si)Ge devices is described, highlighting the impact of the main process parameters on the device electrical characteristics. Finally, the used on-wafer structures are described, with particular focus on a dedicated Poly-Si heater structure, developed for accelerated reliability tests.

Keywords

Charge Pump SiGe Layer Interface State Density Stress Phase Relaxation Transient 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    H. Reisinger et al., Analysis of NBTI degradation–and recovery-behavior based on ultra-fast Vth-measurements, in Proceedings of the IEEE IRPS. p. 448–453, 2006Google Scholar
  2. 2.
    B. Kaczer et al., Disorder-controlled-kinetics model for negative bias temperature instability and its experimental verification, in Proceedings of the IEEE IRPS. p. 381–387, 2005Google Scholar
  3. 3.
    B. Kaczer et al., Ubiquitous relaxation in BTI stressing—new evaluation and insights, in Proceedings of the IEEE IRPS. (Phoenix, USA, 2008), p. 20–27Google Scholar
  4. 4.
    M. Denais et al., On-the-fly characterization of NBTI in ultra-thin gate oxide pMOSFETs, in Proceedings of the IEEE IEDM. (Washington, USA, 2004), pp. 109–112Google Scholar
  5. 5.
    V. Huard, M. Denais, C. Parthasarathy, NBTI degradation: from physical mechanism to modeling. Microelectron. Reliab. 46(1), 1–23 (2006)CrossRefGoogle Scholar
  6. 6.
    T. Grasser, B. Kaczer, Negative bias temperature instability: Recoverable vs. Permanent degradation, in Proceedings of the ESSDERC. p. 127–130, 2007Google Scholar
  7. 7.
    E. Cartier et al., Fundamental aspects of HfO2-based high-k metal gate stack reliability and implications on t inv-scaling, in Proceedings of the IEEE IEDM. p. 18.4.1–4, 2011Google Scholar
  8. 8.
    M. Cho et al., Insight into N/PBTI mechanisms in sub-1 nm EOT devices. IEEE Trans. Electron Dev. 59(8), 2042–2048 (2012)ADSCrossRefGoogle Scholar
  9. 9.
    S. Realov, K.L. Shepard, Random telegraph noise in 45 nm CMOS: analysis using an on-chip test and measurement system, in Proceedings of the IEEE IEDM. (Washington, USA, 2010), p. 624–247Google Scholar
  10. 10.
    G. Groeseneken, H.E. Maes, N. Beltran, R.F. De Keersmaecker, A reliable approach to charge-pumping measurements in MOS transistors. IEEE Trans. Electron Dev. 31(1), 42–53 (1984)CrossRefGoogle Scholar
  11. 11.
    M.G. Ancona, N.S. Saks, D. McCarthy, Lateral distribution of hot-carrier-induced interface traps in MOSFETs. IEEE Trans. Electron Dev. 35(12), 2221–2228 (1988)ADSCrossRefGoogle Scholar
  12. 12.
    A. Hikavyy et al., SiGe SEG growth for buried channel p-MOS devices. ECS Trans. 25(7), 201–210 (2009)CrossRefGoogle Scholar
  13. 13.
    M. Meuris et al., The IMEC clean: A new concept for particle and metal removal on si surfaces. Solid State Technol. 38(7), 109–113 (1995)Google Scholar
  14. 14.
    L.-Å. Ragnarsson et al., Ultra low-EOT (5Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization, in Proceedings of the IEEE IEDM. (Washington, USA, 2009), p. 663–666Google Scholar
  15. 15.
    J. Mitard et al., Sub-nm EOT SiGe-55 % pFETs for high-speed low-VDD technology: a study from capacitor to circuit level, in Proceedings of the IEEE IEDM. (San Francisco, USA, 2010), p. 249–252Google Scholar
  16. 16.
    B. Kaczer et al., Improvements in NBTI reliability of Si-passivated Ge/high-k/metal-gate pFETs. Microelectron. Eng. 86(7–9), 1582–1584 (2009)CrossRefGoogle Scholar
  17. 17.
    Witters et al., 8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS, in Proceedings of IEEE International Symposium on VLSI Technology. p. 181–182, 2010Google Scholar
  18. 18.
    S. Krishnan et al., A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications, in Proceedings of the IEEE IEDM. (Washington, USA, 2011), p. 634–637Google Scholar
  19. 19.
    G. Hellings et al., Implant-free SiGe quantum well pFET: a novel, highly scalable, and low thermal budget device, featuring raised source/drain and high mobility channel, in Proceedings of the IEEE IEDM. (San Francisco, USA, 2010), pp. 241–244Google Scholar
  20. 20.
    M. Caymax et al., The influence of the epitaxial growth process parameters on layer characteristics and device performance in Si-passivated Ge pMOSFETs. J. Electrochem. Soc. 156(12), H979–H985 (2009)CrossRefGoogle Scholar
  21. 21.
    W. Muth, W. Walter, Bias temperature instability assessment of n- and p-channel MOS transistors using a polysilicon resistive heated scribe lane test structure. Microelectron. Reliab. 44(8), 1251–1262 (2004)CrossRefGoogle Scholar
  22. 22.
    T. Aichinger, M. Nelhiebel, T. Grasser, Unambiguous identification of the NBTI recovery mechanism using ultra-fast temperature changes, in Proceedings of the IEEE IRPS. (Montrea, 2009), p. 2–7Google Scholar
  23. 23.
    T. Grasser et al., The paradigm shift in understanding the bias temperature instability: from reaction-diffusion to switching oxide traps. IEEE Trans. Electron Dev. 58(11), 3652–3666 (2011)ADSCrossRefGoogle Scholar
  24. 24.
    G. Pobegen, T. Aichinger, M. Nelhiebel, T. Grasser, Understanding temperature acceleration for NBTI, in Proceedings of the IEEE IEDM. p. 27.3.1–4, 2011Google Scholar
  25. 25.
    V.S. Kannan, PSoC® 3 and PSoC 5LP - Temperature Measurement with a Diode, AN60590, Cypress, www.cypress.com
  26. 26.
    J.R. Lloyd et al., Electromigration failure in thin film silicides and polysilicon/silicide (polycide) structures, in Proceedings of the IEEE IRPS. p. 198–202, 1983Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2014

Authors and Affiliations

  1. 1.IMECLeuvenBelgium

Personalised recommendations