Hardware Implementation of Microprogrammed Controller Based Digital FIR Filter
Digital finite-impulse response (FIR) filter is the fundamental processing element of many digital signal processing (DSP) systems, ranging from wireless communications to image and video processing. The microarchitecture of digital FIR filter consists of a datapath and a control unit. The datapath is the computational engine of FIR filter and mainly consists of adders, multipliers and delay elements. Several techniques have been proposed in the existing literature to implement digital FIR filters in hardware using field programmable gate array (FPGA). In this chapter, hardware implementation of a parallel digital FIR filter architecture using a novel microprogrammed controller is presented. The main advantage of the microprogrammed controller is its flexibility in modifying the microprogram stored in ROM based control memory. To demonstrate the proposed technique, a 4-tap parallel FIR filter is implemented using Virtex-5 FPGA. The proposed FIR filter is coded in VHDL using top-down hierarchical design methodology. Performance evaluation is done based on the implementation results obtained through FPGA synthesis tools. The designed 4-tap FIR filter utilizes minimal area leaving bulk of the FPGA resources to implement other parallel processors on the same device. The design can be easily modified to implement higher-order and high speed FIR filters which are commonly used in video and image processing applications.
KeywordsDigital filter Finite-impulse response (FIR) filter FPGA Hardware Implementation Microprogrammed controller
This work was supported in part by King Abdulaziz City for Science and Technology (KACST) under Project Ejaz (IRU No. 31/513). The authors would like to thank the reviewers for their valuable comments and suggestions to improve the quality of this chapter.
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