Fault-Tolerant Optimization for Application-Specific Network-on-Chip Architecture

  • Farnoosh Hosseinzadeh
  • Nader Bagherzadeh
  • Ahmad Khademzadeh
  • Majid Janidarmian
Chapter
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 247)

Abstract

Advanced integration technologies enable the construction of Network-on-Chip (NoC) from two dimensions to three dimensions. Studies have shown that 3D NoCs can improve average communication performance because of the possibility of using the additional dimension to shorten communication distance. This paper presents a defect tolerance technique for recovering permanent routers failure through an efficient and effective use of redundancy. This technique is ideally suited for three and even two dimensional network-on-chip (NoC). This fault-tolerant NoC architecture designed in VHDL and synthesized using Xilinx ISE is presented. Simulation results demonstrate significant reliability and yield improvement. Although the hardware overhead of the 3D (2D)-proposed methodology compare with traditional mesh is approximately 15 % (12 %), it improves the average response time of system up to 31 % (23 %).

Keywords

Application-specific By-pass Defect tolerant architecture Mapping Network-on- chip Spare router 

References

  1. 1.
    Intel (2008) Intel core i7 processor extreme edition and intel core i7 processor datasheet, vol 1Google Scholar
  2. 2.
  3. 3.
    Dally WJ, Towles B (2001) Route packets, not wires: on-chip interconnection networks. In: Proceedings of the 38th conference on Design automation, June 2001, pp 684–689Google Scholar
  4. 4.
    Jerger NE, Peh L-S (2009) On-chip networks, Synthesis Lectures on Computer Architecture 2009Google Scholar
  5. 5.
    Taylor et al. MB (2002) The RAW microprocessor: a computational fabric for software circuits and general-purpose programs. IEEE Micro 22(6):25–35Google Scholar
  6. 6.
    Sankaralingam et al K (2003) Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture, ISCAGoogle Scholar
  7. 7.
    Hu J, Marculescu R (2003) Energy-aware mapping for tile-based NoC architectures under performance constraints, ASP-DACGoogle Scholar
  8. 8.
    Murali S, De Micheli G (2004) Bandwidth constrained mapping of cores onto NoC architecturesGoogle Scholar
  9. 9.
    Srinivasan K, Chatha KS, Konjevod G (2006) Linear-programming based techniques for synthesis of network-on-chip architectures. IEEE Trans VLSI Syst, AprGoogle Scholar
  10. 10.
    Murali et al. S (2006) Designing application-specific networks on chips with floor plan information, ICCADGoogle Scholar
  11. 11.
    Yan S, Lin B (2008) Application-specific network-on-chip architecture synthesis based on set partitions and Steiner trees, ASPDACGoogle Scholar
  12. 12.
    Yan S, Lin B (2008) Custom networks-on-chip architectures with multicast routing. IEEE Trans VLSI Syst, accepted for publicationGoogle Scholar
  13. 13.
    Weldezion AY, Grange M, Pamunuwa D, Lu Z, Jantsch A, Weerasekera R, Tenhunen H (2009) Scalability of network-on-chip communication architecture for 3D meshes. In: Proceedings of the 3rd ACM/IEEE international Symposium on networks-on-chip (NOCS’09), May 2009Google Scholar
  14. 14.
    Feero B, Pande P (2008) Networks-on-chip in a three-dimensional environment: a performance evaluation. IEEE Trans ComputGoogle Scholar
  15. 15.
    Kim J, Nicopoulos C, Park D, Das R, Xie Y, Vijaykrishnan N, Yousif MS, Das CR (2007) A novel dimensionally-decomposed router for on-chip communication in 3D architectures. In: Proceedings of the international Symposium on computer architecture (ISCA’07), June 2007Google Scholar
  16. 16.
    Bolotin E, Cidon I, Ginosar R, Kolodny A (2004) Cost considerations in network on chip. Integr VLSI J 38(1):19–42CrossRefGoogle Scholar
  17. 17.
    Nassif S (2001) Modeling and analysis of manufacturing variations. Proc CICCGoogle Scholar
  18. 18.
    Pan et al S (2010) IVF, characterizing the vulnerability of microprocessor structures to intermittent faults. ProcGoogle Scholar
  19. 19.
    Constantinescu C (2007) Intermittent faults in VLSI circuits. Proc IEEE Workshop silicon Errors logic (SELSE)Google Scholar
  20. 20.
    Dumitraş T, Mărculescu R (2003) On-chip stochastic communication, vol 1, Design, Automation and test in Europe conference and exhibition, p 10790Google Scholar
  21. 21.
    Hosseinzadeh F, Bagherzadeh N, Khademzadeh A, Janidarmian M, Koupaei FK (2012) Improving reliability in application-specific 3D network-on-chip, lecture notes in engineering and computer science. In: Proceedings of the world congress on engineering and computer science 2012, WCECS 2012, San Francisco, USA, pp 196–202, 24–26 Oct 2012Google Scholar
  22. 22.
    Philip G, Christopher B, Ramm P (2008) Handbook of 3D integration. Wiley-VCH, New YorkGoogle Scholar
  23. 23.
    Davis W et al (2005) Demystifying 3D ICs: the pros and cons of going vertical. IEEE Des Test Comput 22(6):498–510CrossRefGoogle Scholar
  24. 24.
    Jantsch A, Tenhunen H (2003) Networks on chip. Kluwer Academic Publishers, BerlinGoogle Scholar
  25. 25.
    De Micheli G, Benini L (2006) Networks on chips. Morgan Kaufmann, BurlingtonGoogle Scholar
  26. 26.
    Li et al. F (2006) Design and management of 3D chip multiprocessors using network-in-memory. In: Proceedings of international Symposium on computer architecture, pp 130–141, Jun 2006Google Scholar
  27. 27.
    Loi I, Angiolini F, Fujita S, Benini L (2011) Characterization and implementation of fault-tolerant vertical links for 3-D Networks-on-Chip. IEEE Trans Comput Aided Des Integr Circuits Syst 30(1)Google Scholar
  28. 28.
    Pavlidis VF, Friedman EG (2007) 3-D topologies for networks-on- chip. IEEE Trans Very Large Scale Integr (VLSI), pp 1081–1090Google Scholar
  29. 29.
    Feero B, Pande PP Performance evaluation for three-dimensional networks-on-chip. IEEE Comput Soc Annu Symp VLSI (ISVLSI’07)Google Scholar
  30. 30.
    Weldezion AY, Grange M, Weerasekera R, Tenhunen H (2009) Scalability of network-on-chip communication architecture for 3-D meshes, IEEEGoogle Scholar
  31. 31.
    Dumitras T, Kerner S, Marculescu R (2003) Towards on-chip fault tolerant communication. In: Proceedings of the Asia and South Pacific design automation conferenceGoogle Scholar
  32. 32.
    Shi Z, You K, Ying Y, Huang B, Zeng X, Yu Z (2010) A scalable and fault-tolerant routing algorithm for NoCs. Int Symp Circ, pp 165–168Google Scholar
  33. 33.
    Refan F, Alemzadeh H, Safari S, Prinetto P, Navabi Z (2008) Reliability in application specific mesh-based NoC architectures, on-line testing symposium, 14th IEEE International, pp 207–212, Jul 2008Google Scholar
  34. 34.
    Koupaei FK, Khademzadeh A, Janidarmian M (2011) Fault-tolerant application-specific network-on-chip, IEEE 2011Google Scholar
  35. 35.
    Yan S, Lin B (2008) Design of application-specific 3D networks-on-chip architectures. In: Proceedings of ICCD, pp 142–149Google Scholar
  36. 36.
    Murali S, Seiculescu C, Benini L, Micheli GD (2009) Synthesis of networks on chips for 3D systems on chips. In: Proceedings of ASPDAC, pp 242–247Google Scholar
  37. 37.
    Murali et al S (2006) Designing application-specific networks on chips with floor plan information. In: Proceedings of ICCAD, pp 355–362Google Scholar
  38. 38.
    Janidarmian M, Khademzadeh A, Tavanpour M (2009) Onyx: A new heuristic bandwidth-constrained mapping of cores onto tile-based Network on Chip. IEICE Electron Express 6(1):1–7CrossRefGoogle Scholar
  39. 39.
    Palesi M, Holsmark R, Kumar S (2006) A methodology for design of application specific deadlock-free routing algorithms for NoC systems, hardware/software codesign and system synthesis, CODES + ISSS ‘06. In: Proceedings of the 4th international conference, pp 142–147, Oct 2006Google Scholar
  40. 40.
    Janidarmian M, Roshan Fekr A, Samadi Bokharaei V (2011) Application-specific networks-on-chips design. IAENG Int J Comput Sci 38(1):16–25Google Scholar
  41. 41.
    Janidarmian M, Tinati M, Khademzadeh A, Ghavibazou M, Fekr AR (2010) Special issue on a fault tolerant network on chip architecture. AIP Conf Proc 1247:191–204Google Scholar
  42. 42.
    Wang LT, Stroud CE, Touba NA (2008) System-on-chip test architectures, nanometer design for testability, Mogran Kauffmann, BurlingtonGoogle Scholar
  43. 43.
    Dally WJ, Towles B (2003) Principles and practice of interconnection networks. Morgan Kaufmann, BurlingtonGoogle Scholar
  44. 44.
    Shamshiri S, Cheng KTT (2011) Modeling yield, cost, and quality of a spare-enhanced multi-core chip. IEEE Trans ComputGoogle Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2014

Authors and Affiliations

  • Farnoosh Hosseinzadeh
    • 1
  • Nader Bagherzadeh
    • 2
  • Ahmad Khademzadeh
    • 3
  • Majid Janidarmian
    • 1
  1. 1.Science and Research BranchIslamic Azad UniversityTehranIran
  2. 2.University of CaliforniaIrvineUSA
  3. 3.Iran Telecommunication Research CenterTehranIran

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