Real Time Video Implementation on FPGA

Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 240)

Abstract

Nowadays, real time video becomes popular in a lot of multimedia equipment, video cameras, tablets, camcorders. The more hardware improved the more application is used. Requesting a faster and cost-effective systems there are triggers a shift to Field Programmable Gate Arrays (FPGAs), where the inherent parallelism results in better performance. The implementation is based on efficient utilization of embedded multipliers and look up table (LUT) of target device to improve speed but also saves the general purpose resources of the target device. This paper proposes new hardware architecture for capture NTSC/PAL video stream. The whole system is implemented on a single low cost FPAG chip, capable of real time procession at frequency 60 MHz. In addition, to increase real-time performance, hardware architecture with streamlined data flow are developed.

Keywords

FPGA Video processing Image processing Real time processing 

References

  1. 1.
    Abutaleb MM, Hamdy A, Saad EM (2008) FPGA-based real time video object segmentation with optimization schemes. Int J Circ Syst Signal Process 2:78–86Google Scholar
  2. 2.
    Jiang H, Owall V, Ardo H (2006) Real-time video segmentation with VGA resolution and memory bandwidth reduction. In: Proceeding of the IEEE international conference on video and signal based surveillance, SydneyGoogle Scholar
  3. 3.
    Lapalme FX, Amer A, Wang C (2006) FPGA architecture for real-time video noise estimation. In: IEEE international conference on image processing. Atlanta, pp 3257–3260Google Scholar
  4. 4.
    Chen PP, Ye A (2011) The effect of multi-bit correlation on the design of field-programmable gate array routing resources. IEEE Trans VLSI Syst 19:283–294Google Scholar
  5. 5.
    Cho J, Jin S, Kwon KH, Jeon JW (2010) A real-time histogram equalization system with automatic gain control using FPGA TIIS 633–654Google Scholar
  6. 6.
    DE2-115 user manual (2011)Google Scholar
  7. 7.
    Altera (2011) Introduction to the Altera SOPC builder using verilog designsGoogle Scholar
  8. 8.
    Altera (2011) Using the SDRAM on Altera’s DE2-115 board with verilog designsGoogle Scholar
  9. 9.
    Jin S, Cho J, Pham XD, Lee KM, Park SK, Jeon JW (2010) FPGA design and implementation of a real-time stereo vision system. IEEE Trans Circ Syst Video Technol 20:15–26Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht(Outside the USA) 2013

Authors and Affiliations

  1. 1.School of Electrical EngineeringUniversity of UlsanUlsanKorea

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