An Intra Prediction Hardware Architecture with Low Computational Complexity for HEVC Decoder
In this paper, hardware architecture with shared operation unit, common operation unit and fast smoothing decision algorithm is proposed to reduce computational complexity of intra prediction in HEVC decoder. The shared operation unit shares adders computing common operations in smoothing equations to remove the computational redundancy and pre-computes the mean value of reference pixels for removing an idle cycle in DC mode. The common operation unit uses one operation unit to generate predicted pixels and filters predicted pixels in all prediction modes to reduce the number of operation units for each mode. The decision algorithm uses only bit-comparators instead of arithmetic operators. The architecture is synthesized using TSMC 0.13um CMOS technology. The gate count and the maximum operating frequency of the architecture are 40.5 k and 164 MHz, respectively. The number of processing cycles of the architecture for one 4 × 4 PU is one cycle and about 93.7 % less than the previous one.
KeywordsHEVC Video coding Intra prediction Shared operation unit Common operation unit Fast smoothing decision algorithm
This research was financially supported by the Ministry of Education, Science Technology (MEST) and National Research Foundation of Korea (NRF) through the Human Resource Training Project for Regional Innovation. This work was sponsored by ETRI SW-SoC R&BD Center, Human Resource Development Project.
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