A Hardware Design for Binary Image Recognition

Chapter
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 229)

Abstract

Recently, nonlinear composite correlation filters have been proposed for distortion-invariant pattern recognition. The filter design is based on logical operations and the correlation is computed with a nonlinear operation called morphological correlation. In this paper a new implementation in parallel hardware of these kinds of filters for image recognition is proposed. The architecture is designed for a Field Programmable Gate Array (FPGA) device. The proposed design performs the most time consuming task of the recognition procedure. In consequence, it reduces the time required for the nonlinear operations in the spatial domain. Simulation results are provided and discussed.

Keywords

FPGA Morphological correlation Nonlinear filters  Parallelprocessing Pattern recognition Programmable devices 

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Copyright information

© Springer Science+Business Media Dordrecht 2013

Authors and Affiliations

  1. 1.División de Estudios de Posgrado e InvestigaciónInstituto Tecnológico de La Paz.La PazMéxico

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