Advertisement

Byte-Addressable Persistent RAM APIs for Flexible Memory Management and Protection

  • Hidayat Febiansyah
  • Jin Baek Kwon
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 214)

Abstract

Byte-addressable persistent random access memory (BPRAM) provides uninterruptable computing experience at power loss. Since there is no need of power to store the data, it is possible to provide faster booting time from completely off-state by utilizing BPRAM as the main memory. However, there is still no explicit explanation about the BPRAM application programming interfaces (APIs) specification taking benefit of the persistent characteristic of the memory. Providing APIs at the operating system level will open possibility to the application and operating system developers to utilize persistent memory to its extent. We defined APIs specifications which include memory management and protection, as some application should not be abusing the BPRAM of its limited lifetime. We focused on phase-change memory (PCM) as the representation of BPRAM, since it is the most probable candidate for DRAM replacement. We observed there are room for improvements to elongate BPRAM lifetime, such as the shared library objects loading to the BPRAM, separation of three memory region in process (i.e. code, data, stack regions), moving rarely modified blocks of RAM to the BPRAM, and also the capability of saving only important states when desired.

Keywords

Persistent memory Phase change memory API Byte-addressable persistent RAM 

References

  1. 1.
    Samsung Electronics Co., Ltd.: Highest Density Mobile LPDDR2 Memory, using 20 nm-class Technology. http://www.samsung.com/global/business/semiconductor/news-events/press-releases/detail?newsId=10941. Mei 2012
  2. 2.
    Conditt, J., et al.: Better I/O through byte-addressable, persistent memory. In: SIGOPS 22nd Symposium on Operating Systems Principles (2009)Google Scholar
  3. 3.
    Bailey, K., et al.: Operating system implications of fast, cheap, non-volatile memory. In: Proceedings of the 13th USENIX Conference on Hot Topics in Operating Systems (2011)Google Scholar
  4. 4.
    Joshi, M., et al.: Mercury: A fast and energy-efficient multi-level cell based phase change memory system. In: High Performance Computer Architecture (HPCA) 2011Google Scholar
  5. 5.
    Song, N.H., et al.: Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping. In: Proceeding of the 37th Annual International Symposium on Computer Architecture (2010)Google Scholar
  6. 6.
    Ferreira, A.P., et al.: Increasing PCM main memory lifetime. In: Design, Automation & Test in Europe Conference & Exhibition (DATE) (2010)Google Scholar
  7. 7.
    Jiang, L., et al.: LLS: Cooperative integration of wear-leveling and salvaging for PCM main memory. In: Dependable Systems & Networks (DSN) (2011)Google Scholar
  8. 8.
    Quraishi, M.K., et al.: Enhancing lifetime and security of pcm-based main memory with start-gap wear leveling. In: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (2009)Google Scholar
  9. 9.
    Joo, Y., et al.: Energy- and endurance-aware design of phase change memory caches. In: Design, Automation & Test in Europe Conference & Exhibition (DATE) (2010)Google Scholar
  10. 10.
    Chang, M.F., et al.: Challenges and trends in low-power 3D die-stacked IC designs using RAM, memristor logic, and resistive memory (ReRAM). In: The IEEE International Conference on ASIC (ASICON) (2011)Google Scholar
  11. 11.
    Lee, B.C., et al.: Phase change memory architecture and the quest for scalability. ACM. Mag. (7) 53(7), 99–106 (2010)Google Scholar
  12. 12.
    Jiang, L., et al.: Improving write operations in MLC phase change memory. In: High Performance Computer Architecture (HPCA) (2012)Google Scholar
  13. 13.
    Zhou, P,. et al.: A durable and energy efficient main memory using phase change memory technology. In: Poceeding of the 36th Annual International Symposium on Computer Architecture (2009)Google Scholar
  14. 14.
    Quraishi, M.K., et al.: Practical and secure PCM-based main-memory system via online attack detection, attack detection. In: Workshop on the Use of Emerging Storage and Technologies, co-located with HPCA (2010)Google Scholar
  15. 15.
    Dhiman, G., et al.: PDRAM: a hybrid PRAM and DRAM main memory system. In: Proceedings of the 46th Annual Design Automation Conference (DAC ‘09) (2009)Google Scholar
  16. 16.
    Choi, I.H., et al.: Wear leveling for PCM Using hot data identification. In: International Conference on IT Convergence and Security 2011Google Scholar
  17. 17.
    Zhang, T., et al.: Leveraging on-chip DRAM stacking in an embedded 3D multi-core DSP system. In: IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1–4 (2011)Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2013

Authors and Affiliations

  1. 1.Department of Computer Science and EngineeringSun Moon UniversityCheonan Republic of Korea

Personalised recommendations