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An Operation Scheduling Technique for Coarse Grained Reconfigurable Architectures

  • Yongjoo Kim
  • Jongwon Lee
  • Doosan Cho
  • Yunheung Paek
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 214)

Abstract

To provide efficiency of high performance and low power, CGRA (Coarse-Grained Reconfigurable Architectures) is becoming a very popular component in embedded systems. However, compiler support does not reach the quality of provided hardware efficiency. To remedy CGRA system’s such weakness, this paper proposes a compiler directed instruction and data mapping technique for two dimensional mesh based CGRAs. The proposed approach uses IDFG (Instruction-Data Flow Graph) to represent the relationship between instructions and array data. Each node of IDFG assigns to processing cores and sets of data blocks to on-chip memories. During the mapping process, the on-chip memory capacity and the topology of the interconnection among processing cores are taken into account to minimize routing length since it determines the completion time of loop kernels and energy consumption. By using IDFG in mapping process, the instruction and data mapping can be combined as a unified framework. The experimental evaluation shows that our IDFG based mapping technique are very successful in practice, achieving almost optimal results.

Notes

Acknowledgments

This work was supported in part by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (No.2011-0027005), the Engineering Research Center of Excellence Program(Grant 2012-0000470), the Korea Science and Engineering Foundation (KOSEF) NRL Program (No. 0421-2012-0047) of Korea Ministry of Education, Science and Technology (MEST), and the Center for Integrated Smart Sensors funded by the MEST as Global Frontier Project (CISS-0543-20110012).

References

  1. 1.
    Park, H., Fan, K., Mahlke, S.A., Oh, T., Kim, H., Kim, H.-S.: Edge-centric modulo scheduling for coarse-grained reconfigurable architectures. In: Proceedings of the 17th International Conference on Parallel Architectures and Compilation, Techniques, pp. 166–176 (2008)Google Scholar
  2. 2.
    Ramakrishna Rau, B.: Iterative modulo scheduling: an algorithm for software pipelining loops. In: Proceedings of the 27th Annual International Symposium on Microarchitecture, MICRO, vol. 27, pp. 63–74 (1994)Google Scholar
  3. 3.
    Paek, Y., Hoeflinger, J., Padua, D.: Simplification of array access patterns for compiler optimizations. In: Proceedings of the ACM SIGPLAN 1998 Conference on Programming Language Design and Implementation, PLDI ’98 (1998)Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2013

Authors and Affiliations

  • Yongjoo Kim
    • 1
  • Jongwon Lee
    • 1
  • Doosan Cho
    • 2
  • Yunheung Paek
    • 1
  1. 1.School of EECSSeoul National UniversitySeoulKorea
  2. 2.Department of Electronic EngineeringSunchon National UniversitySuncheonKorea

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