NAND and Controller Co-design for SSDs

Chapter
Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 37)

Abstract

SSD is made up by NAND Flash memories, DRAMs and a NAND controller. To realize a low-power high-speed SSD, the overall performance of the NAND Flash memory and the NAND controller should be optimized by co-designing both NAND and controller circuits. This chapter describes the most advanced circuits in this field.

Furthermore, 3D-integration in the SSD system becomes a key topic and an example of low power 3D-integrated SSD is shown.

Finally, a couple of techniques, Asymmetric Coding and Stripe Pattern Elimination Algorithm, for reducing the NAND raw BER are presented.

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Copyright information

© Springer Science+Business Media Dordrecht 2013

Authors and Affiliations

  1. 1.Department of Electrical, Electronic and Communication EngineeringChuo UniversityTokyoJapan

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