Abstract
In this chapter, low-density parity-check (LDPC) codes, a class of powerful iteratively decodable error correcting codes, are introduced. The chapter first reviews some basic concepts and results in information theory such as Shannon’s channel capacity and channel coding theorem. It then overviews the Flash memory channel model. Finally, it addresses LDPC codes describing both their structure and efficient implementation, and their decoding algorithms. Simulation results are also provided.
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
The capacity of the BSC only depends on the crossover probability and not on the values assumed by X and Y.
- 2.
For unstructured ensemble, the minimum variable and check nodes are usually set to 2. The reason for this choice is out of the scope of this chapter.
- 3.
- 4.
The words “horizontal” and “vertical” remind us that the check nodes and the variable nodes are associated with the rows and the columns of the parity-check matrix, respectively.
References
S. Abu-Surra, D. Divsalar, W.E. Ryan, Enumerators for protograph-based ensembles of LDPC and generalized LDPC codes. IEEE Trans. Inf. Theory 57(February), 858–886 (2011)
C. Berrou, A. Glavieux, P. Thitimajshima, Near shannon limit error-correcting coding and decoding: turbo-codes, in Proceedings of the 2003 International Conference on Communication, vol. 2, May 1993, Geneva, Switzerland, pp. 1064–1070
N. Bonello, S. Chen, L. Hanzo, Low-density parity-check codes and their rateless relatives. IEEE Commun. Surveys & Tutorials 13(February), 3–26 (2011)
D. Cavus, C. Haymes, Low BER performance estimation of LDPC codes via application of importance sampling to trapping sets. IEEE Trans. Commun. 57(July), 1886–1888 (2009)
L. Chen, J. Xu, I. Djurdjevic, S. Lin, Near Shannon limit quasi cyclic low-density parity-check codes. IEEE Trans. Commun. 52(July), 1038–1042 (2004)
J. Chen, M. Tanner, C. Jones, Y. Li, Improved min-sum decoding algorithms for irregular LDPC codes, in Proceedings of the 2005 IEEE International Symposium on Information Theory, Sept 2005, Adelaide, Australia, pp. 449–453
J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier, X.-Y. Hu, Reduced-complexity decoding of LDPC codes. IEEE Trans. Commun. 53(August), 1288–1299 (2005)
M. Chiani, A. Ventura, Design and performance evaluation of some high-rate irregular low-density parity-check codes, in Proceedings of the 2001 Global Telecommunication Conference, San Antonio, TX, Nov 2001, pp. 990–994
S.-Y. Chung, G.D. Forney Jr., T. Richardson, R. Urbanke, On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit. IEEE Commun. Lett. 5(February), 58–60 (2001)
T.M. Cover, J.A. Thomas, Elements of Information Theory (Wiley, New York, 1991)
L. Dolecek et al., Predicting error floors of structured LDPC codes: Deterministic bounds and estimates. IEEE J. Sel. Areas Commun. 27(August), 908–917 (2009)
M. Flanagan, E. Paolini, M. Chiani, M. Fossorier, On the growth rate of the weight distribution of irregular doubly-generalized LDPC codes. IEEE Trans. Inf. Theory 57(June), 3721–3737 (2011)
M. Fossorier, Quasi-cyclic low-density parity-check codes from circulant permutation matrices. IEEE Trans. Inf. Theory 50(August), 1788–1793 (2004)
R.D. Fowler, L. Nordheim, Electron emission in intense electric fields. Proc. Royal Soc. London 119(May), 173–181 (1928)
R.G. Gallager, Low-Density Parity-Check Codes (MIT Press, Cambridge, 1963)
X.-Y. Hu, M. Fossorier, E. Eleftheriou, On the computation of the minimum distance of low-density parity-check codes, in Proceedings of the 2004 International Conference on Communication, June 2004, Paris, France, pp. 767–771
S. Li, T. Zhang, Improving multi-level NAND flash memory storage reliability using concatenated BCH-TCM coding. IEEE Trans. VLSI 18(October), 1412–1420 (2010)
Z. Li, L. Chen, L. Zeng, S. Lin, W. Fong, Efficient encoding of low-density parity-check codes. IEEE Trans. Commun. 54(January), 71–81 (2006)
G. Liva, M. Chiani, Protograph LDPC codes design based on EXIT analysis, in Proceedings of the 2007 IEEE Global Telecommunications Conference, Washington, DC, Nov 2007, pp. 3250–3254
M. Mansour, High-performance decoders for regular and irregular repeat-accumulate codes, in Proceedings of the IEEE 2004 IEEE Global Telecommunications Conference, Nov/Dec 2004, Dallas, TX, USA, pp. 2583–2588
R. Micheloni, L. Crippa, A. Marelli (eds.), Inside NAND Flash Memories (Springer, Berlin, 2010)
N. Mielke et al., Bit error rate in NAND Flash memories, in Proceedings of the 2008 IEEE International Symposium on Reliability Physics, Phoenix, AZ, Apr/May 2008, pp. 9–19
T. Richardson, Error floors of LDPC codes, in Proceedings of the 41st Annual Allerton Conference on Communication, Control and Computing, (Monticello, IL, USA, 2003)
T. Richardson, M. Shokrollahi, R. Urbanke, Design of capacity-approaching irregular low-density parity-check codes. IEEE Trans. Inf. Theory 47(February), 619–637 (2001)
T. Richardson, R. Urbanke, The capacity of low-density parity-check codes under message-passing decoding. IEEE Trans. Inf. Theory 47(February), 599–618 (2001)
T. Richardson, R. Urbanke, The renaissance of Gallager’s low-density parity-check codes. IEEE Commun. Mag. 41(August), 126–131 (2003)
H. Tang, J. Xu, Y. Kou, S. Lin, K. Abdel-Ghaffar, On algebraic construction of Gallager and circulant low density parity-check codes. IEEE Trans. Inf. Theory 50(June), 1269–1279 (2004)
M. Tanner, A recursive approach to low complexity codes. IEEE Trans. Inf. Theory 27(September), 533–547 (1981)
S. ten Brink, Convergence behavior of iteratively decoded parallel concatenated codes. IEEE Trans. Commun. 49(October), 1727–1737 (2001)
J. Thorpe, Low-density parity-check (LDPC) codes constructed from protographs. JPL INP, Tech. Rep. August 42–154 (2003)
J. Xu, L. Chen, L. Zeng, L. Lan, S. Lin, Construction of low-density parity-check codes by superposition. IEEE Trans. Commun. 53(February), 243–251 (2005)
J. Wang, T. Courtade, H. Shankar, R. Wesel, Soft information for LDPC decoding in flash: Mutual-information optimized quantization, in Proceedings of the 2011 IEEE Global Telecommunication Conference, Houston, TX, Dec 2011
J. Zhao, F. Zarkeshvari, A. Banihashemi, On implementation of min-sum algorithm and its modifications for decoding low-density parity-check (LDPC) codes. IEEE Trans. Commun. 53(April), 549–554 (2005)
Acknowledgment
The author wishes to thank Prof. M. Chiani (University of Bologna) and Dr. G. Liva (DLR) for their useful feedback. He also wishes to thank Ing. R. Micheloni and A. Marelli (IDT Italy) for their careful proof check of this chapter.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2013 Springer Science+Business Media Dordrecht
About this chapter
Cite this chapter
Paolini, E. (2013). Low-Density Parity-Check (LDPC) Codes. In: Inside Solid State Drives (SSDs). Springer Series in Advanced Microelectronics, vol 37. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-5146-0_11
Download citation
DOI: https://doi.org/10.1007/978-94-007-5146-0_11
Published:
Publisher Name: Springer, Dordrecht
Print ISBN: 978-94-007-5145-3
Online ISBN: 978-94-007-5146-0
eBook Packages: EngineeringEngineering (R0)