On-Chip PT Sensor Circuits for Minimum Data Retention Voltage

  • Kyung Ki Kim
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 181)


This paper proposes on-chip process and temperature sensor circuits to find a minimum data retention voltage in nanoscale CMOS systems. The process variation is monitored by the low cost gate tunneling leakage sensor, and the temperature is monitored using a zero temperature coefficient (ZTC) principle. The minimum data-retention voltage of flip-flops for low power operation is generated for different temperature and process corner conditions adaptively using a look-up-table method based on the simple PT monitoring circuits. The proposed circuits are implemented using 45 nm CMOS predictive technology model.


On-chip PT sensor Process variation Temperature variation Zero temperature coefficient (ZTC) Data retention voltage 


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Copyright information

© Springer Science+Business Media Dordrecht 2012

Authors and Affiliations

  1. 1.Department of Electronic EngineeringDaegu UniversityGyeongsanSouth Korea

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