On-Chip PT Sensor Circuits for Minimum Data Retention Voltage

Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 181)

Abstract

This paper proposes on-chip process and temperature sensor circuits to find a minimum data retention voltage in nanoscale CMOS systems. The process variation is monitored by the low cost gate tunneling leakage sensor, and the temperature is monitored using a zero temperature coefficient (ZTC) principle. The minimum data-retention voltage of flip-flops for low power operation is generated for different temperature and process corner conditions adaptively using a look-up-table method based on the simple PT monitoring circuits. The proposed circuits are implemented using 45 nm CMOS predictive technology model.

Keywords

On-chip PT sensor Process variation Temperature variation Zero temperature coefficient (ZTC) Data retention voltage 

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References

  1. 1.
    Bowman, K., et al.: Impact of die-to-die and within-die parameter fluctuations onthe maximum clock frequency distribution for gigascale integration. IEEE Journal of Solid-State Circuits, 183–190 (2002)Google Scholar
  2. 2.
    Borkar, S.: Parameter variations and impact on circuits & microarchitecture. C2S2MARCO Review (2003)Google Scholar
  3. 3.
    Sery, G., et al.: Life is CMOS: why chase the life after? In: IEEE DAC, pp. 78–83 (2002)Google Scholar
  4. 4.
    Karnik, T., et al.: Sub-90 nm technologies, challenges and opportunities for CAD. In: IEEE ICCAD, pp. 203–206 (2002)Google Scholar
  5. 5.
    Shaheer, A., Kameyama, M.: Real-time threshold-voltage control scheme forlow-power VLSI under fluctuation of a supply voltage. In: ISSCS 2005, vol. 1, pp. 15–18 (2005)Google Scholar
  6. 6.
    Ajami, A.H., Banerjee, K., et al.: Analysis of IR-drop scaling with implications fordeep submicron PG network designs. In: Quality Electronic Design 2003, pp. 35–40 (2003)Google Scholar
  7. 7.
    Seomun, J., Shin, Y.: Design and optimization of power-gated circuits withautonomous data-retention. IEEE Transactions on Very Large Scale Integration Systems 19(2), 227–236 (2011)CrossRefGoogle Scholar
  8. 8.
    Roy, K., Hsu, S., Krishnamurthy, R.K., Borkar, S.: On-die CMOS leakage currentsensor for measuring process variation in sub-90nm generations. In: IEEE Symposium on VLSI Circuits, pp. 250–251 (2004)Google Scholar
  9. 9.
    Chang, M.-H., Liu, C.-P., Huang, H.-P.: Chip implementation with combined temperature sensor and reference devices based on DZTC principle. IET Electronics Letters 46(13), 1–2 (2010)CrossRefGoogle Scholar
  10. 10.
    Zhao, W., Liu, F., Agarwal, K., et al.: Rigorous extraction of process variationsfor 65-nm CMOS design. IEEE Transactions on Semiconductor Manufacturing 22(1), 196–203 (2009); Wang, S., Wolf, W. et al.: Accurate stacking macro-modeling of leakage power insub-100 nm circuits. In: IEEE VLSID, pp. 165–170 (2005)Google Scholar
  11. 11.
    Shima, T.: Temperature insensitive current reference circuit using standard CMOS devices. In: IEEE MWSCAS 2007, pp. 181–184 (2007)Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2012

Authors and Affiliations

  1. 1.Department of Electronic EngineeringDaegu UniversityGyeongsanSouth Korea

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