A PVT-Aware and Low Power Pulse-Triggered Flip-Flop
In this paper, a new low power inverse delay element which can be used in all pulse-triggered flip-flops to decrease power consumption with no effects on timing characteristics is proposed. Through combinational utilization of the proposed low power inverse delay element, conditional capture technique and conditional keeper technique, a novel flip-flop is designed. This novel flip-flop overcomes power-consuming defect of pulse-triggered flip-flop while retains the property of negative setup time and thus provides short data-to-output delay and tolerability to clock edge uncertainty caused by PVT variation. The simulation comparison results based on SMIC 90nm technology indicate that in comparison to six typical high performance flip-flops, the proposed flip-flop features the best power-delay-product (PDP) with typical input activity of 0.4. Its maximum PDP improvement against counterpart is up to 72%. Furthermore, when input activity is greater than 0.2, it obtain the lowest power consumption with slight impact on delay, its maximum power saving is up to 27%. Therefore the proposed Flip-Flop is suitable for low power and high performance application.
Keywordslow power flip-flops latches clock distribution synchronous digital system PVT-aware
Unable to display preview. Download preview PDF.
- 5.Ko, U., Hill, A., Balsara, P.T.: Design techniques for high performance, energy-efficient control logic. In: ISLPED Dig. Tech. Papers (Aug. 1996)Google Scholar
- 6.Partovi, H., Burd, R., Salim, U., Weber, F., DiGregorio, L., Draper, D.: Flow-through latch and edge-triggered flip-flop hybrid elements. In: ISSCC Dig. Tech. Papers, pp. 138–139 (February 1996)Google Scholar
- 7.Klass, F.: Semi-dynamic and dynamic flip-flops with embedded logic. In: 1998 Symp. VLSI Circuits Dig. Tech. Papers, Honolulu, HI, June 11-13, pp. 108–109 (1998)Google Scholar
- 10.Nedovic, N., Oklobdzija, V.G.: Hybrid latch flip-flop with improved power efficiency. In: Proceedings of SBCCI, pp. 211–215 (September 2000)Google Scholar
- 13.Joshi, V., Blaauw, D., Sylvester, D.: Soft-edge flip-flops for improved timing yield: Design and optimization. In: Proc. Int. Conf. Comput. Aided Des., pp. 667–673 (November 2007)Google Scholar
- 14.Nedovic, N., Oklobdzija, V.: Dynamic flip-flop with improved power. In: Proc. Int. Conf. Computer Design, pp. 323–326 (September 2000)Google Scholar
- 15.Oklobdzija, V.G.: Clocking in multi-GHz environment. In: Proc. 23rd IEEE Int. Conf. Microelectronics, vol. 2, pp. 561–568 (2002)Google Scholar