A PVT-Aware and Low Power Pulse-Triggered Flip-Flop

Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 181)

Abstract

In this paper, a new low power inverse delay element which can be used in all pulse-triggered flip-flops to decrease power consumption with no effects on timing characteristics is proposed. Through combinational utilization of the proposed low power inverse delay element, conditional capture technique and conditional keeper technique, a novel flip-flop is designed. This novel flip-flop overcomes power-consuming defect of pulse-triggered flip-flop while retains the property of negative setup time and thus provides short data-to-output delay and tolerability to clock edge uncertainty caused by PVT variation. The simulation comparison results based on SMIC 90nm technology indicate that in comparison to six typical high performance flip-flops, the proposed flip-flop features the best power-delay-product (PDP) with typical input activity of 0.4. Its maximum PDP improvement against counterpart is up to 72%. Furthermore, when input activity is greater than 0.2, it obtain the lowest power consumption with slight impact on delay, its maximum power saving is up to 27%. Therefore the proposed Flip-Flop is suitable for low power and high performance application.

Keywords

low power flip-flops latches clock distribution synchronous digital system PVT-aware 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Kawaguchi, H., Sakurai, T.: A reduced clock-swing flip-flop (RCSFF) for 63% power reduction. IEEE J. Solid-State Circuits 33, 807–811 (1998)CrossRefGoogle Scholar
  2. 2.
    Unger, S.H., et al.: Clocking schemes for high-speed digital systems. IEEE Trans. Comput. C-35, 880–895 (1986)CrossRefGoogle Scholar
  3. 3.
    Stojanovic, V., et al.: Comparative analysis of master–slave latches and flip–flops for high-performance and low-power systems. IEEE J. Solid State Circuits 34, 536–548 (1999)CrossRefGoogle Scholar
  4. 4.
    Gerosa, G., Gary, S., Dietz, C., Dac, P., Hoover, K., Alvarez, J., Sanchez, H., Ippolito, P., Tai, N., Litch, S., Eno, J., Golab, J., Vanderschaaf, N., Kahle, J.: A 2.2 W, 80 MHz superscalar RISC microprocessor. IEEE J. Solid-State Circuits 29, 1440–1452 (1994)CrossRefGoogle Scholar
  5. 5.
    Ko, U., Hill, A., Balsara, P.T.: Design techniques for high performance, energy-efficient control logic. In: ISLPED Dig. Tech. Papers (Aug. 1996)Google Scholar
  6. 6.
    Partovi, H., Burd, R., Salim, U., Weber, F., DiGregorio, L., Draper, D.: Flow-through latch and edge-triggered flip-flop hybrid elements. In: ISSCC Dig. Tech. Papers, pp. 138–139 (February 1996)Google Scholar
  7. 7.
    Klass, F.: Semi-dynamic and dynamic flip-flops with embedded logic. In: 1998 Symp. VLSI Circuits Dig. Tech. Papers, Honolulu, HI, June 11-13, pp. 108–109 (1998)Google Scholar
  8. 8.
    Qiao, F., Yang, H., Wei, D., Wang, H.: Low-standby-current and high-speed SAFF with improved conditional-precharge modules. Journal of Circuits, Systems and Computers (JCSC) 16(2), 199–210 (2007)CrossRefGoogle Scholar
  9. 9.
    Kong, B., Kim, S., Jun, Y.: Conditional-capture flip-flop for statistical power reduction. IEEE J. Solid-State Circuits 36(8), 1263–1271 (2001)CrossRefGoogle Scholar
  10. 10.
    Nedovic, N., Oklobdzija, V.G.: Hybrid latch flip-flop with improved power efficiency. In: Proceedings of SBCCI, pp. 211–215 (September 2000)Google Scholar
  11. 11.
    Zhao, P., Darwish, T., Bayoumi, M.: High-performance and low power conditional dis-charge flip-flop. IEEE Trans. Very Large Scale Integr (VLSI) Syst. 12(5), 477–484 (2004)CrossRefGoogle Scholar
  12. 12.
    Teh, C.K., Hamada, M., Fujita, T., Hara, H., Ikumi, N., Oowaki, Y.: Conditional data mapping flip-flops for low-power and high-performance systems. IEEE Trans. Very Large Scale Integr (VLSI) Systems 14, 1379–1383 (2006)CrossRefGoogle Scholar
  13. 13.
    Joshi, V., Blaauw, D., Sylvester, D.: Soft-edge flip-flops for improved timing yield: Design and optimization. In: Proc. Int. Conf. Comput. Aided Des., pp. 667–673 (November 2007)Google Scholar
  14. 14.
    Nedovic, N., Oklobdzija, V.: Dynamic flip-flop with improved power. In: Proc. Int. Conf. Computer Design, pp. 323–326 (September 2000)Google Scholar
  15. 15.
    Oklobdzija, V.G.: Clocking in multi-GHz environment. In: Proc. 23rd IEEE Int. Conf. Microelectronics, vol. 2, pp. 561–568 (2002)Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2012

Authors and Affiliations

  1. 1.Institute of Circuits and Systems, Dept. of Electronic Engineering, Tsinghua National Laboratory for Information Science and TechnologyTsinghua UniversityBeijingP.R. China

Personalised recommendations