A PVT-Aware and Low Power Pulse-Triggered Flip-Flop

Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 181)


In this paper, a new low power inverse delay element which can be used in all pulse-triggered flip-flops to decrease power consumption with no effects on timing characteristics is proposed. Through combinational utilization of the proposed low power inverse delay element, conditional capture technique and conditional keeper technique, a novel flip-flop is designed. This novel flip-flop overcomes power-consuming defect of pulse-triggered flip-flop while retains the property of negative setup time and thus provides short data-to-output delay and tolerability to clock edge uncertainty caused by PVT variation. The simulation comparison results based on SMIC 90nm technology indicate that in comparison to six typical high performance flip-flops, the proposed flip-flop features the best power-delay-product (PDP) with typical input activity of 0.4. Its maximum PDP improvement against counterpart is up to 72%. Furthermore, when input activity is greater than 0.2, it obtain the lowest power consumption with slight impact on delay, its maximum power saving is up to 27%. Therefore the proposed Flip-Flop is suitable for low power and high performance application.


low power flip-flops latches clock distribution synchronous digital system PVT-aware 


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© Springer Science+Business Media Dordrecht 2012

Authors and Affiliations

  1. 1.Institute of Circuits and Systems, Dept. of Electronic Engineering, Tsinghua National Laboratory for Information Science and TechnologyTsinghua UniversityBeijingP.R. China

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