The Impact of Cache on Memory Test

  • Die Hu
  • Junmin Wu
  • Xiaodong Zhu
  • Yinbing Wang
  • Bangjie Jiang
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 181)

Abstract

In order to ensure the reliability of embedded systems, test of the embedded system memory is particularly important. Among the different types of algorithms proposed for testing memories, March test is the most popular one. Due to directly accessing memory, during the memory test, cache must be turned off, which greatly reduces the speed of memory access. In accordance with the characteristics of MPC8572 development platform and the memory fault models, we propose a method to speed up March test which takes advantage of cache to store data from memory for the CPU. However, turning on cache can mask many memory fault models. CPU can’t directly access memory, which causes memory test results inaccurate. In this paper, we focus on the impact of cache on memory test and analyze how cache can mask the memory fault models. Then, bases on this analysis, we propose a method to speed up March test. For different March operations, configuring the cache speeds up the memory test.

Keywords

Cache Fault Model March Algorithm 

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References

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Copyright information

© Springer Science+Business Media Dordrecht 2012

Authors and Affiliations

  • Die Hu
    • 1
  • Junmin Wu
    • 1
    • 2
  • Xiaodong Zhu
    • 1
  • Yinbing Wang
    • 2
  • Bangjie Jiang
    • 1
  1. 1.Department of Computer Science and TechnologyUniversity of Science and Technology of ChinaHefeiChina
  2. 2.Suzhou Institute for Advanced StudyUniversity of Science and Technology of ChinaSuzhouChina

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