A Low Latency Variance NoC Router

Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 181)

Abstract

Network on chip has emerged as a promising way to replace traditional shared buses for better scalability and design reusability. The dominant problem posed by this packet-switched fabric is the potentially-high latency and communication uncertainty. Various router architectures have been developed to reduce the average network delay. However few attentions are paid to the communication uncertainty yet more critical to overall system performance. This paper points out the inefficiency of ignoring packet latency variance just by reducing the average latency. A priority based technique is proposed in this paper to reduce the latency variance by an age-based and deadline-based arbiter that can dynamically adjust packets’ priority at run-time without prior knowledge of the application type. The latency variance can be reduced by 14% ~ 35% with the proposed arbiter and adaptive routing in a middle injection rate while maintains the average latency to the same level.

Keywords

Chip Multiprocessor (CMP) Many Core Processor Network on Chip (NoC) 

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References

  1. 1.
    Benini, L., Micheli, G.D.: Networks on chips: a new SoC paradigm. Computer 35(1), 70–78 (2002), doi:10.1109/2.976921CrossRefGoogle Scholar
  2. 2.
    Dally, W.J., Towles, B.: Route packets, not wires: On-chip interconnection networks. In: DAC 2001: 38th Design Automation Conference 2001, pp. 684–689, 171 (2001)Google Scholar
  3. 3.
    Taylor, M.B., Kim, J., Miller, J., et al.: The Raw microprocessor: a computational fabric for software circuits and general-purpose programs. IEEE-MICRO 22(2), 25–35 (2002), doi:10.1109/mm.2002.997877CrossRefGoogle Scholar
  4. 4.
    Bell, S., Edwards, B., Amann, J., et al.: TILE64 - Processor: A 64-Core SoC with Mesh Interconnect. In: IEEE International Solid-State Circuits Conference 2008, pp. 88–598 (2008)Google Scholar
  5. 5.
    Vangal, S., Howard, J., Ruhl, G., et al.: An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS. In: IEEE International Solid-State Circuits Conference 2007, pp. 98–589 (2007)Google Scholar
  6. 6.
    Howard, J., Dighe, S., Vangal, S.R., et al.: A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. IEEE J. Solid-State Circuit 46(1), 173–183 (2011), doi:10.1109/jssc.2010.2079450CrossRefGoogle Scholar
  7. 7.
    Kumar, A., Peh, L.S., Kundu, P., et al.: Express Virtual Channels: Towards the Ideal Interconnection Fabric. In: ISCA 2007: 34th Annual International Symposium on Computer Architecture 2011, pp. 150–161, 11 (2007)Google Scholar
  8. 8.
    Matsutani, H., Koibuchi, M., Amano, H., et al.: Prediction router: Yet another low latency on-chip router architecture. In: HPCA 2009: IEEE 15th International Symposium on High Performance Computer Architecture 2009, pp. 367–378 (2009)Google Scholar
  9. 9.
    Mullins, R., West, A., Moore, S.: Low-latency virtual-channel routers for on-chip networks. In: ISCA 2004: 31st Annual International Symposium on Computer Architecture 2004, pp. 188–197, 8 (2004)Google Scholar
  10. 10.
    Mullins, R., West, A., Moore, S.: The design and implementation of a low-latency on-chip network. In: ASP-DAC 2006: 11th Asia and South Pacific Design Automation Conference 2006, pp. 164–169, 9 (2006)Google Scholar
  11. 11.
    Kim, J., Nicopoulos, C., Park, D., et al.: A gracefully degrading and energy-efficient modular router architecture for on-chip networks. In: ISCA 2006: 33rd International Symposium on Computer Archtiecture 2006, pp. 4–15, 2 (2006)Google Scholar
  12. 12.
    Peh, L.S., Dally, W.J.: A delay model and speculative architecture for pipelined routers. In: HPCA 2001: 7th International Symposium on High-Performance Computer Architecture 2001, pp. 255–266 (2001)Google Scholar
  13. 13.
    Park, D., Das, R., Nicopoulos, C., et al.: Design of a dynamic priority-based fast path architecture for on-chip interconnects. In: 15th Annual IEEE Symposium on High-Performance Interconnects 2007, pp. 15–20, 0 (2007)Google Scholar
  14. 14.
    Michelogiannakis, G., Pnevmatikatos, D., Katevenis, M.: Approaching ideal NoC latency with pre-configured routes. In: 1st International Symposium on Networks-on-Chip 2007, pp. 153–162, 1 (2007)Google Scholar
  15. 15.
    Li, Z., Wu, J., Shang, L., et al.: Latency criticality aware on-chip communication. In: DATE 2009: Design, Automation & Test in Europe Conference & Exhibition 2009, pp. 1052–1057 (2009)Google Scholar
  16. 16.
    Mraz, R.: Reducing the variance of point to point transfers in the IBM 9076. In: The ACM/IEEE Supercomputing 1994 Conference 1994, pp. 620–629 (1994)Google Scholar
  17. 17.
    Kim, J., Dally, W.J., Abts, D.: Adaptive Routing in High-Radix Clos Network. In: The ACM/IEEE Supercomputing 2006 Conference 2006, p. 7 (2006)Google Scholar
  18. 18.
    Dally, W.J.: Virtual-channel flow control. In: ISCA 1990: 17th Annual International Symposium on Computer Architecture 1990, pp. 60–68 (1990)Google Scholar
  19. 19.
    Intel: Pentium® Pro Family Developer’s Manual, Specifications, vol. 1, pp. 137–142 (1996) Google Scholar
  20. 20.
    Qian, Y., Lu, Z.H., Dou, W.H.: Analysis of Worst-case Delay Bounds for Best-effort Communication in Wormhole Networks on Chip. In: 3rd ACM/IEEE International Symposium on Networks-on-Chip 2009, pp. 44–53, 2 (2009)Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2012

Authors and Affiliations

  1. 1.Institute of Circuits and Systems, Dept. of Electronic Engineering, TNlistTsinghua UniversityBeijingChina

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