A Low Latency Variance NoC Router

Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 181)


Network on chip has emerged as a promising way to replace traditional shared buses for better scalability and design reusability. The dominant problem posed by this packet-switched fabric is the potentially-high latency and communication uncertainty. Various router architectures have been developed to reduce the average network delay. However few attentions are paid to the communication uncertainty yet more critical to overall system performance. This paper points out the inefficiency of ignoring packet latency variance just by reducing the average latency. A priority based technique is proposed in this paper to reduce the latency variance by an age-based and deadline-based arbiter that can dynamically adjust packets’ priority at run-time without prior knowledge of the application type. The latency variance can be reduced by 14% ~ 35% with the proposed arbiter and adaptive routing in a middle injection rate while maintains the average latency to the same level.


Chip Multiprocessor (CMP) Many Core Processor Network on Chip (NoC) 


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Copyright information

© Springer Science+Business Media Dordrecht 2012

Authors and Affiliations

  1. 1.Institute of Circuits and Systems, Dept. of Electronic Engineering, TNlistTsinghua UniversityBeijingChina

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