Overhead- and Performance-Aware Fault-Tolerant Architecture for Application-Specific Network-on-Chip

  • Fathollah Karimi Koupaei
  • Ahmad Khademzadeh
  • Majid Janidarmian
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 170)


Defect in manufacturing of integrated circuits is almost inevitable, and fast scaling in technology has caused the components of a Network-on-Chip (NoC) to be more susceptible to faults. Therefore, it is crucial to sustain chip production yield and reliable operation in the presence of defects. The permanent faults are a consequence of manufacturing defects that occur during fabrication or aging defects that occur during system lifetime. A fault-tolerant application-specific NoC should be able to detect a fault and recover the system to correctly operate the mapped application. In this paper, a fault-tolerant NoC architecture designed in VHDL and synthesized using Xilinx ISE is presented which not only is able to recover from single permanent router failure, but also improves the average response time of the system in the different traffic loads. As hardware overhead is a major issue while considering fault tolerance, a new component, called Link Interface (LI) is also developed to reduce cost overhead. The Video Object Plan Decoder (VOPD) and MPEG-4 core graphs are used as two real applications in this study.


Application-specific network-on-chip Deadlock-free routing algorithm Fault-tolerant design Link interface Mapping algorithm Permanent failure 


  1. 1.
    Benini L (2006) Application specific NoC design, date. In: Proceedings of the design automation & test in Europe conference, vol 1. p 105Google Scholar
  2. 2.
    Shen W, Chao C, Lien Y, Wu A (2007) A new binomial mapping and optimization algorithm for reduced-complexity mesh-based on-chip network, NOCS. In: First international symposium on networks-on-chip (NOCS’07), pp 317–322Google Scholar
  3. 3.
    RoshanFekr A, Janidarmian M, Samadi Bokharaei V, Khademzadeh A (2011) Yield enhancement with a novel method in design of application-specific networks on chips. Electr Eng Appl Comput 90:247–257CrossRefGoogle Scholar
  4. 4.
    Furber S (2008) The future of computer technology and its implications for the computer industry. Comput J 51(6):735–740CrossRefGoogle Scholar
  5. 5.
    Borkar S (2005) Designing reliable systems from unreliable components: the challenges of transistor variability and degradation. IEEE Micro 25(6):10–16Google Scholar
  6. 6.
    Dumitraş T, Mărculescu R (2003) On-chip stochastic communication, date. In: Design, automation and test in Europe conference and exhibition (DATE’03), vol 1. p 10790Google Scholar
  7. 7.
    Karimi Koupaei F, Khademzadeh A, Janidarmian M (2011) Fault-tolerant application-specific network-on-chip. Lecture notes in engineering and computer science: proceedings of the world congress on engineering and computer science 2011, WCECS 2011, San Francisco, USA, pp 734–738, 19–21 Oct 2011Google Scholar
  8. 8.
    Shivakumar P, Kistler M, Keckler SW, Burger D, Alvisi L (2002) Modeling the effect of technology trends on the soft error rate of combinational logic. dsn. In: International conference on dependable systems and networks (DSN’02), p 389Google Scholar
  9. 9.
    Ali M, Welzl M, Hessler S, Hellebrand S (2007) An Efficient fault tolerant mechanism to deal with permanent and transient failures in a network on chip. Int J High Perform Sys Archit 1(2):113–123CrossRefGoogle Scholar
  10. 10.
    Rantala V, Lehtonen T, Liljeberg P, Plosila J (2009) Multi network interface architectures for fault tolerant network-on-chip, isscs. International symposium on signals, circuits and systems. pp 1–4Google Scholar
  11. 11.
    Zou Y, Pasricha S (2010) NARCO: neighbor aware turn model-based fault tolerant routing for NoCs. Embed Sys Lett IEEE 2:85–89CrossRefGoogle Scholar
  12. 12.
    Dumitras T, Kerner S, Marculescu R (2003) Towards on-chip fault-tolerant communication. In: Proceedings of the Asia and South Pacific design automation conferenceGoogle Scholar
  13. 13.
    Shi Z, You K, Ying Y, Huang B, Zeng X, Yu Z (2010) A scalable and fault-tolerant routing algorithm for NoCs, iscas. International symposium on circuits and systems (ISCAS), 30 May 2010–2 June 2010, pp 165–168Google Scholar
  14. 14.
    Refan F, Alemzadeh H, Safari S, Prinetto P, Navabi Z (2008) Reliability in application specific mesh-based NoC architectures. On-line testing symposium, 2008. IOLTS apos; 08. 14th IEEE international, pp 207–212Google Scholar
  15. 15.
    Janidarmian M, Tinati M, Khademzadeh A, Ghavibazou M, RoshanFekr A (2010) Special issue on a fault tolerant network on chip architecture. AIP Conf Proc 1247:191–204CrossRefGoogle Scholar
  16. 16.
    Janidarmian M, Khademzadeh A, Tavanpour M (2009) Onyx: a new heuristic bandwidth-constrained mapping of cores onto tile-based network on chip. IEICE Electron Express 6(1):1–7CrossRefGoogle Scholar
  17. 17.
    Janidarmian M, Samadi Bokharaie V, Khademzadeh A, Tavanpour M (2010) Sorena: new on chip network topology featuring efficient mapping and simple deadlock free routing algorithm. 2010 10th IEEE international conference on computer and information technology, pp 2290–2299Google Scholar
  18. 18.
    Janidarmian M, RoshanFekr A, Samadi Bokharaei V (2011) Application-specific networks-on-chips design. IAENG Int J Comp Sci 38(1):16–25Google Scholar
  19. 19.
    Palesi M, Holsmark R, Kumar S (2006) A methodology for design of application specific deadlock-free routing algorithms for NoC systems. Hardware/software codesign and system synthesis, CODES + ISSS ‘06. In: Proceedings of the 4th international conference, pp 142–147, Oct 2006Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2013

Authors and Affiliations

  • Fathollah Karimi Koupaei
    • 1
  • Ahmad Khademzadeh
    • 2
  • Majid Janidarmian
    • 3
  1. 1.CE DepartmentArak Branch of Azad UniversityArakIran
  2. 2.Iran Telecommunication Research CenterTehranIran
  3. 3.CE DepartmentScience and Research Branch of Azad UniversityTehranIran

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