Overhead- and Performance-Aware Fault-Tolerant Architecture for Application-Specific Network-on-Chip

  • Fathollah Karimi Koupaei
  • Ahmad Khademzadeh
  • Majid Janidarmian
Chapter
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 170)

Abstract

Defect in manufacturing of integrated circuits is almost inevitable, and fast scaling in technology has caused the components of a Network-on-Chip (NoC) to be more susceptible to faults. Therefore, it is crucial to sustain chip production yield and reliable operation in the presence of defects. The permanent faults are a consequence of manufacturing defects that occur during fabrication or aging defects that occur during system lifetime. A fault-tolerant application-specific NoC should be able to detect a fault and recover the system to correctly operate the mapped application. In this paper, a fault-tolerant NoC architecture designed in VHDL and synthesized using Xilinx ISE is presented which not only is able to recover from single permanent router failure, but also improves the average response time of the system in the different traffic loads. As hardware overhead is a major issue while considering fault tolerance, a new component, called Link Interface (LI) is also developed to reduce cost overhead. The Video Object Plan Decoder (VOPD) and MPEG-4 core graphs are used as two real applications in this study.

Keywords

Application-specific network-on-chip Deadlock-free routing algorithm Fault-tolerant design Link interface Mapping algorithm Permanent failure 

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Copyright information

© Springer Science+Business Media Dordrecht 2013

Authors and Affiliations

  • Fathollah Karimi Koupaei
    • 1
  • Ahmad Khademzadeh
    • 2
  • Majid Janidarmian
    • 3
  1. 1.CE DepartmentArak Branch of Azad UniversityArakIran
  2. 2.Iran Telecommunication Research CenterTehranIran
  3. 3.CE DepartmentScience and Research Branch of Azad UniversityTehranIran

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