The Co-Design of Test Structure and Test Data Transfer Mode for 2D-Mesh NoC

Chapter
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 170)

Abstract

NoC(Network-on-Chip) has been proposed as a new solution to deal with the global communication problem of complex SoC(System-on-Chip). However, there are many difficulties in testing and verification for NoC. We propose novel co-design of test architecture and data transfer schemes for 2D-Mesh topology NoC to improve the parallelism of test packets transmission. The testing efficiencies of different structures or transfer modes are evaluated under a coverage-driven and hierarchical NoC testbench, which is based on the VMM verification methodology and SystemVerilog language. The evaluation results of testing cost, testing time and hardware overhead show that the shortening of transmission path and parallel testing effectively decreases the power consumption and testing time. Furthermore, one of these test structures can be proved to the optimal scheme.

Keywords

Data transfer NoC Parallel testing Testbench Test structure VMM 

Notes

Acknowledgments

This work was supported by the Natural Science Foundation of China under Grant 61076019 and 61106018, the Aeronautical Science Foundation of China under Grant 20115552031, the China Postdoctoral Science Foundation under Grant 20100481134.

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Copyright information

© Springer Science+Business Media Dordrecht 2013

Authors and Affiliations

  1. 1.The College of Information Science and TechnologyNanjing University of Aeronautics and AstronauticsNanjingChina

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