Development of a Bottom-up Compact Model for Intel®’s High-K 45 nm MOSFET

  • David E. Espejo Rodriguez
  • Alba G. Ávila Bernal
Chapter
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 170)

Abstract

MOSFETs models have been critical components for evaluation of devices design and technology. These models face the challenge of being scalable to match the available semiconductor technologies. For the 45 nm MOSFET production, dielectric and metal gates were integrated. With new high dielectric materials and thinner oxide layers, new physics effects emerged that were not considered or integrated into the early models used in circuit simulators. Here an analytical model for 45 nm MOSFETs is presented. The model includes Short Channel Effects (Channel Length Modulation, the threshold voltage variation and carriers velocity saturation). The Drain-Source current and voltage equations derived from the model are implemented as a circuit device in SPICE 3F5. A comparison between the experimental data provided by the manufacturer and the simulation results obtained with the developed model integrating the technological and electrical parameters published by Intel®, demonstrates good agreement between both sets of data.

Keywords

Compact High-K Model MOSFET Short channel effects SPICE 

References

  1. 1.
    Moore G (1965) Cramming more components onto integrated circuits. Electronics 38(8):114–117Google Scholar
  2. 2.
    University of California, Irvine, Department of Electrical Engineering and Computer Science, HSPICE User’s Manual, 2007Google Scholar
  3. 3.
    Vladimirescu A, Lius S (1980) Simulation of MOS using SPICE2. Electronics Research Laboratory, University of California, BerkeleyGoogle Scholar
  4. 4.
    Mississippi State University (2005) MOSFET devices and their SPICE models. Department of Electrical and Computer EngineeringGoogle Scholar
  5. 5.
    Ytterdal T, Cheng Y, Fjeldly T (2003) Device modeling for analog and RF CMOS circuit design, Wiley online libraryGoogle Scholar
  6. 6.
    Ávila A, Espejo D (2011) A SPICE-compatible model for intel®’s high-k 45 nm MOSFET. Lecture notes in engineering and computer science: proceedings of the world congress on engineering and computer science 2011, WCECS 2011, San Francisco, USA, pp 762–765, 19–21 OctoberGoogle Scholar
  7. 7.
    Inaba S, Okano K, Izumida T, Kaneko A, Kawasaki A, Yagishita A, Kanemura T, Ishida T, Aoki N, Ishimaru K, Suguro K, Eguchi K, Tsunashima Y, Toyoshima Y, Ishiuchi H (2006) FinFET: the prospective multi-gate device for future SoC applications. In: Proceedings of the 36th European solid-state device research conferenceGoogle Scholar
  8. 8.
    Song J, Choi W, Park J, Lee J, Park B (2006) Design optimization of gate-all-around (GAA) MOSFETs. IEEE Trans Nanotechnol 5(3):186–191CrossRefGoogle Scholar
  9. 9.
    Auth C, Capellani J, Dalis A, Ghani T, Mistry K (2009) 45 nm high-k + metal gate strain-enhanced transistors. Intel PressGoogle Scholar
  10. 10.
    Intel™ Press (2008) A 45 nm logic technology with high-k + metal gate transistors, strained silicon, 9 cu interconnect layers, 193 nm dry patterning, and 100 % Pb-free packagingGoogle Scholar
  11. 11.
    Hergenrother JM et al (2000) The vertical replacement-gate (VRG) MOSFET: a high performance vertical MOSFET with lithography-independent critical dimensions IEEE Electron Devices MeetingGoogle Scholar
  12. 12.
    Kavalieros J, Doyle B, Datta S, Dewey G, Doczy M, Jin B, Lionberger D, Metz M, Rachmady W, Radosavljevic M, Shah U, Zelick N, Chau R (2006) Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering. Symposium on VLSI technology digest of technical papersGoogle Scholar
  13. 13.
    Doyle BS, Datta S, Doczy M (2003) High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Device Lett 24(4):263–265CrossRefGoogle Scholar
  14. 14.
    Bohr M, Chau R, Ghani T, Mistry K (2007) The high-k solution. IEEE Spectr 44(10):23–29CrossRefGoogle Scholar
  15. 15.
    Ming L (2007) Semi-empirical device model for nanoscale MOSFET. PhD thesis, Universiti Teknologi MalaysiaGoogle Scholar
  16. 16.
    Wang L (2006) Quantum mechanical effects on MOSFET scaling limit. PhD thesis, School of Electrical and Computer Engineering, Georgia Institute of TechnologyGoogle Scholar
  17. 17.
    Hareland SA, Manassian M, Shih WK, Jallepalli S, Wang H, Chindalore GL, Tasch A, Maziar CM (1998) Computationally efficient models for quantization effects in MOS electron and hole accumulation layers. IEEE Trans Electron Devices 45(7):1487–1493CrossRefGoogle Scholar
  18. 18.
    Vasileska D, Ahmed S, Mannino M, Matsudaira A, Klimeck G, Lundstrom M SCHRED, available on http://nanohub.org/resources/schred
  19. 19.
    Ren Z (2001) Nanoscale MOSFETs: physics, simulation and design. PhD thesis, Purdue UniversityGoogle Scholar
  20. 20.
    University of California, Berkeley, Arizona State University, Berkeley Predictive Technology Model, available on http://ptm.asu.edu/modelcard/LP/45nm_LP.pm, retrieved on 26/04/10
  21. 21.
    Mistry K, Allen C, Auth C (2007) A 45 nm logic technology with High-k metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning and 100 % free Pb packaging, IEDMGoogle Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2013

Authors and Affiliations

  • David E. Espejo Rodriguez
    • 1
  • Alba G. Ávila Bernal
    • 1
  1. 1.Microelectronics CenterUniversidad de los AndesBogotáColombia

Personalised recommendations