Adaptive Three-Bit LDPC Decoder Quantization

  • Raymond Moberly
  • Michael E. O’Sullivan
  • Khurram Waheed
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 170)


This chapter presents two related 3-bit quantizations for the sum-product algorithm that are suitable for an adaptive decoder implementation using programmable logic. Our decoder design combines the parity-check and variable-node-update steps into a single computation. The hardware requirements are considered and compared to the published work of Planjery et al. Decoder performance in the waterfall region is obtained by simulation.


Belief propagation Finite precision Iterative decoding Low density parity check codes Nonlinear quantization Sum-product algorithm 



This research was supported in part by NSF grants CCF 0635382 and CHE 0216563. FPGA hardware and development tools were provided by the Altera Corporation. The authors acknowledge Shiva Planjery’s graciousness in providing simulation results of their proprietary decoder using the LDPC code that we constructed.


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Copyright information

© Springer Science+Business Media Dordrecht 2013

Authors and Affiliations

  • Raymond Moberly
    • 1
  • Michael E. O’Sullivan
    • 1
  • Khurram Waheed
    • 1
  1. 1.San Diego State UniversitySan DiegoUSA

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