Novel Hybrid Silicon/CNT 4T SRAM Cell Design

Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 164)


With CMOS technology scaling down, static random access memories (SRAMs) consume more than 90 % of chip area and power consumption in modern microprocessor designs and system-on-chip applications. In order to achieve lower power consumption and less area for SRAMs, 4T SRAM structure can be used. However, the conventional silicon 4T SRAM suffers low static noise margin (SNM) and other stability issues compared with commonly used 6T SRAM. In order to improve the SNM and the robustness of 4T SRAM, in this paper we propose a novel hybrid silicon/carbon nanotube (CNT) 4T SRAM structure. The latch transistors in silicon 4T SRAM structure are replaced with carbon nanotube field effect transistors (CNFETs). The proposed design reduces 58 % cell area compared with silicon 6T SRAM and features improved performance and stability compared with silicon 4T SRAM. With the benefits of low OFF current and high ON current from CNFET devices, the proposed hybrid 4T SRAM has 8.3x faster reading speed, 2.5x faster writing speed, 34.5 % reduction for reading power and 24 % reduction for writing power compared with silicon 4T SRAM. The SNM of the proposed design is increased to 6x and 1.11x compared with silicon 4T and 6T SRAM respectively.


SRAM Carbon nanotube CNFET Hybrid Circuit structure 


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Copyright information

© Springer Science+Business Media Dortdrecht 2012

Authors and Affiliations

  1. 1.Department of Electrical and Computer EngineeringIllinois Institute of TechnologyChicagoUSA

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