Design and Management of VFI Partitioned Networks-on-Chip

Chapter
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 184)

Abstract

The design of many core systems-on-chip (SoCs) has become increasingly challenging due to high levels of integration, excessive energy consumption, and clock distribution problems. To deal with these issues, this chapter considers network-on-chip (NoC) architectures partitioned into several voltage-frequency islands (VFIs) and propose a design methodology for runtime energy management. The proposed approach minimizes the energy consumption subject to performance constraints. Then, we present efficient techniques for on-the-fly workload monitoring and management to ensure that the system can cope with variability in the workload and various technology-related parameters. Finally, the results and functional correctness are validated using an FPGA prototype for an NoC with multiple VFIs.

References

  1. 1.
    Arjomand M, Sarbazi-Azad H (2010) Voltage-frequency planning for thermal-aware, low-power design of regular 3-D NoCs. In: 23rd international conferene on VLSI designGoogle Scholar
  2. 2.
    Bertozzi D et al (2005) NoC synthesis flow for customized domain specific multiprocessor systems-on-chip. IEEE Trans Parallel Distrib Syst 16(2):113–129CrossRefGoogle Scholar
  3. 3.
    Bjerregaard T, Sparso J (2005) A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip. In: Proceedings of design, automation and test in Europe conference, March 2005Google Scholar
  4. 4.
    Bogdan P, Marculescu R (2010) Workload characterization and its impact on multicore platform design. In: Proceedings of the 8th IEEE/ACM/IFIP international conferene on hardware/software codesign and system synthesis (CODES/ISSS)Google Scholar
  5. 5.
    Butts JA, Sohi GS (2000) A static power model for architects. In: Proceedings of international symposium of microarchitecture, Dec 2000Google Scholar
  6. 6.
    Burd TD, Brodersen RW (2000) Design issues for dynamic voltage scaling. In: International symposium on low power electronics and designGoogle Scholar
  7. 7.
    Campobello G, Castano M, Ciofi C, Mangano D (2006) GALS networks on chip: a new solution for asynchronous delay-insensitive links. In: Proceedings of design, automation and test in Europe conference, March 2006Google Scholar
  8. 8.
    Chelcea T, Nowick SM (2000) A low latency fifo for mixed-clock systems. In: Proceedings of IEEE computer society workshop on VLSI, April 2000Google Scholar
  9. 9.
    Chapiro DM (1984) Globally asynchronous locally synchronous systems. PhD thesis, Stanford UniversityGoogle Scholar
  10. 10.
    Coskun AK et al (2010) Energy-efficient variable-flow liquid cooling in 3D stacked architectures. In: Proceedings of design automation and test in Europe, pp 1–6Google Scholar
  11. 11.
    Dasgupta S, Yakovlev A (2007) Comparative analysis of GALS clocking schemes. IET Comput Digit Tech 1(2):59–69CrossRefGoogle Scholar
  12. 12.
    Dhillon YS, Diril AU, Chatterjee A, Lee HS (2003) Algorithm for achieving minimum energy consumption in CMOS circuits using multiple supply and threshold voltages at the module level. In: Proceedings of international conference on computer aided design, Nov 2003Google Scholar
  13. 13.
    Dick R Embedded system synthesis benchmarks suites (E3S). http://ziyang.eecs.umich.edu/~dickrp/e3s/
  14. 14.
    Dielissen J, Radulescu A, Goossens K, Rijpkema E (2003) Concepts and implementation of the philips network-on-chip. IP-based SoC designGoogle Scholar
  15. 15.
    Duarte DE, Vijaykrishnan N, Irwin MJ (2002) A clock power model to evaluate impact of architectural and technology optimizations. IEEE Trans Very Large Scale Integr Syst 10(6):884–855Google Scholar
  16. 16.
    Garg S, Marculescu D, Marculescu R (2010) Custom feedback control: enabling truly scalable on-chip power management for MPSoCs. In: Proceedings of the ACM/IEEE international, symposium on low power electronics and design, Austin, TXGoogle Scholar
  17. 17.
    Ge Y, Malani P, Qiu Q (2010) Distributed task migration for thermal management in many-core systems. In: Design automation conference, Anaheim, June 2010Google Scholar
  18. 18.
    Hu J, Marculescu R (2005) Communication and task scheduling of application-specific networks-on-chip. IEE Proc Comput Digit Tech 152(5):643–651Google Scholar
  19. 19.
    Hu J, Marculescu R (2005) Energy- and performance-aware mapping for regular NoC architectures. IEEE Trans Comput Aided Des Integr Circuits Syst 24(4):551–562CrossRefGoogle Scholar
  20. 20.
    Intel Corp. Enhanced Intel® SpeedStep® Technology for the Intel® Pentium® M Processor. http://download.intel.com/design/network/papers/30117401.pdf. Accessed March 2004
  21. 21.
  22. 22.
    Juang P, Wu Q, Peh L, Martonosi M, Clark D (2005) Coordinated, distributed, formal energy management of chip multiprocessors. In: Proceedings of the ISLPED, Aug 2005Google Scholar
  23. 23.
    Lackey DE, Zuchowski PS, Bednar TR, Stout DW, Gould SW, Cohn JM (2002) Managing power and performance for system-on-chip designs using voltage islands. In: Proceedings of international conference on computer aided design, Nov 2002Google Scholar
  24. 24.
    Magklis G, Semeraro G, Albonesi DH, Dropsho SG, Dwarkadas S, Scott ML (2003) Dynamic frequency and voltage scaling for a multiple clock domain microprocessor. IEEE Micro Special Issue: Top Picks Comput Archit 23(6):62–68Google Scholar
  25. 25.
    Martin S, Flautner K, Mudge T, Blaauw D (2002) Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads. In: Proceedings of international conference on computer aided design, Nov 2002Google Scholar
  26. 26.
    Matlab ® Documentation Optimization Toolbox, fmincon. http://www.mathworks.com/
  27. 27.
    Millberg M, Nilsson E, Thid R, Kumar S, Jantsch A (2004) The Nostrum backbone—a communication protocol stack for networks on chip. In: Proceedings of VLSI design, Jan 2004Google Scholar
  28. 28.
    Muttersbach J, Villager T, Fichtner W (2000) Practical design of globally asynchronous locally synchronous systems. In: Proceedings of international symposium on advanced research in asynchronous circuits and systems, April 2000Google Scholar
  29. 29.
    Nash SG, Sofer A (1996) Linear and nonlinear programming. McGraw-Hill, New YorkGoogle Scholar
  30. 30.
    National Semiconductor Corporation (2004) Next-generation SoC power management with multi-domain adaptive voltage scaling. Electronics product design, March 2004Google Scholar
  31. 31.
    Niyogi K, Marculescu D (2005) Speed and voltage selection for GALS systems based on voltage/frequency islands. In: Proceedings of Asia and South Pacific design automation conference, Jan 2005Google Scholar
  32. 32.
    Ogata K (1995) Discrete-time control systems. Prentice-Hall, Upper Saddle RiverGoogle Scholar
  33. 33.
    Sharifi S et al (2010) Hybrid dynamic energy and thermal management in heterogeneous embedded multiprocessor SoCs. In: Asia and south pacific design automation conference, pp 873–878, Jan 2010Google Scholar
  34. 34.
    Rasmussen J (1998) Nonlinear programming by cumulative approximation refinement. Struct Multidiscip Optim 15(1):1–7MathSciNetCrossRefGoogle Scholar
  35. 35.
    Quartana J, Renane S, Baixas A, Fesquet L, Renaudin M (2005) GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. In: Proceedings of international conference on field programmable logic and applications, Aug 2005Google Scholar
  36. 36.
    Sakurai T, Newton AR (1990) Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE J Solid-State Circuits 25(2):584–594CrossRefGoogle Scholar
  37. 37.
    Schittkowski K (1986) NLPQL: a fortran subroutine solving constrained nonlinear programming problems. Ann Oper Res 5(1–4):485–500Google Scholar
  38. 38.
    Semiconductor Association (2006) The international technology roadmap for semiconductors (ITRS)Google Scholar
  39. 39.
  40. 40.
    Toshiba America Electronic Components, Inc. Impact of multiple-voltage domain (Multi-VDD) design implementation on large, complex SoCs. White paper. http://www.toshiba.com/taec/adinfo/socworld/images/Pointers_Pitfalls_MultiVDD.pdf
  41. 41.
    Wu Q, Juang P, Martonosi M, Clark DW (2004) Formal online methods for voltage/frequency control in multiple clock domain microprocessors. In: Proceedings of the international conference on architectural support for programming languages and operating systems, Oct 2004Google Scholar
  42. 42.
    Xie F, Martonosi M, Malik S (2004) Intraprogram dynamic voltage scaling: bounding opportunities with analytic modeling. ACM Trans Archit Code Optim 1(3):323–367Google Scholar
  43. 43.
    Ye T, Benini L, De Micheli G (2002) Analysis of power consumption on switch fabrics in network routers. In: Proceedings of design automation conference, June 2002Google Scholar
  44. 44.
    Zanini F, Atienza D, De Micheli G (2009) A control theory approach for thermal balancing of MPSoC. In: Proceedings of the Asia and south pacific design automation conferenceGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.Intel CorporationHillsboroUSA
  2. 2.Department of Electrical and Computer EngineeringCarnegie Mellon UniversityPittsburghUSA

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