Design and Management of VFI Partitioned Networks-on-Chip

Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 184)


The design of many core systems-on-chip (SoCs) has become increasingly challenging due to high levels of integration, excessive energy consumption, and clock distribution problems. To deal with these issues, this chapter considers network-on-chip (NoC) architectures partitioned into several voltage-frequency islands (VFIs) and propose a design methodology for runtime energy management. The proposed approach minimizes the energy consumption subject to performance constraints. Then, we present efficient techniques for on-the-fly workload monitoring and management to ensure that the system can cope with variability in the workload and various technology-related parameters. Finally, the results and functional correctness are validated using an FPGA prototype for an NoC with multiple VFIs.


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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.Intel CorporationHillsboroUSA
  2. 2.Department of Electrical and Computer EngineeringCarnegie Mellon UniversityPittsburghUSA

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