Analysis and Optimization of Prediction-Based Flow Control in Networks-on-Chip

  • Umit Y. Ogras
  • Radu Marculescu
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 184)


While networks-on-Chip (NoC) architectures may offer higher bandwidth compared to traditional bus-based communication, their performance can degrade significantly in the absence of effective flow control algorithms. This chapter presents a predictive closed-loop flow control mechanism, which is used to predict the congestion level in the network. Based on this information, the proposed scheme controls the packet injection rate at traffic sources in order to regulate the total number of packets in the network. Finally, simulations and experimental study using our FPGA prototype show that the proposed controller delivers a better performance compared to the traditional switch-to-switch flow control algorithms under various real and synthetic traffic patterns.


  1. 1.
    Adriahantenaina A, Greiner A (2003) Micro-network for SoC: implementation of a 32-Port SPIN network. In: Proceedings of design, automation and test in Europe conference, March 2003Google Scholar
  2. 2.
    Baydal E, Lopez P, Duato J (2005) A family of mechanisms for congestion control in wormhole networks. IEEE Trans Parallel Distrib Syst 16(9):772–784Google Scholar
  3. 3.
    Bertsekas D, Gallager R (1992) Data networks. Prentice Hall, Upper Saddle RiverGoogle Scholar
  4. 4.
    Chien AA (1998) A cost and speed model for k-ary n-cube wormhole routers. IEEE Trans Parallel Distrib Syst 9(2):150–162CrossRefGoogle Scholar
  5. 5.
    Dally WJ, Towles B (2004) Principles and practices of interconnection networks. Morgan Kaufmann, San FransiscoGoogle Scholar
  6. 6.
    Dally WJ (1992) Virtual-channel flow control. IEEE Trans Parallel Distrib Syst 3(2):194–205CrossRefGoogle Scholar
  7. 7.
    Dally WJ, Towles B (2001), Route packets, not wires: on-chip interconnection networks. In: Proceedings of design automation conference, June 2001Google Scholar
  8. 8.
    Duato J, Yalamanchili S, Ni L (2002) Interconnection networks: an engineering approach. Morgan Kaufmann, San MateoGoogle Scholar
  9. 9.
    Gerla M, Kleinrock L (1980) Flow control: a comparative survey. IEEE Trans Commun 28(4):553–574CrossRefGoogle Scholar
  10. 10.
    Harmanci M, Escudero N, Leblebici Y, Ienne P (2004) Providing QoS to connection-less packet-switched NoC by implementing DiffServ functionalities. In: Proceedings of international symposium on system-on-chip, November 2004Google Scholar
  11. 11.
    Harmanci M, Escudero N, Leblebici Y, Ienne P (2005) Quantitative modeling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip. In: Proceedings of the international symposium on circuits and systems, May 2005Google Scholar
  12. 12.
    Hedetniemi SM, Hedetniemi ST, Liestman AL (1988) A survey of gossiping and broadcasting in communication networks. Networks 18(4):319–349MathSciNetMATHCrossRefGoogle Scholar
  13. 13.
    Hu J, Marculescu R (2005) Energy- and performance-aware mapping for regular NoC architectures. IEEE Trans Comput Aided Des Integr Circ Syst 24(4):551–562CrossRefGoogle Scholar
  14. 14.
    Hyatt C, Agrawal DP (1997) Congestion control in the wormhole-routed torus with clustering and delayed deflection. In: Proceedings of parallel computing, routing and communication workshopGoogle Scholar
  15. 15.
    Jalabert A, Murali S, Benini L, De Micheli G (2004) XpipesCompiler: a tool for instantiating application specific networks on chip. In: Proceedings of design, automation and test in Europe conference, February 2004Google Scholar
  16. 16.
    Lee HG, Chang N, Ogras UY, Marculescu R (2007) On-chip communication architecture exploration: a quantitative evaluation of point-to-point, bus and network-on-chip approaches. ACM Trans Des Autom Electron Syst 12(3):23Google Scholar
  17. 17.
    Lopez P, Martinez JM, Duato J (1998) DRIL: dynamically reduced message injection limitation mechanism for wormhole networks. In: Proceedings of international conference parallel processing, August 1998Google Scholar
  18. 18.
    Mendel JM (1995) Lessons in estimation theory for signal processing, communications, and control. Prentice-Hall, Upper Saddle RiverMATHGoogle Scholar
  19. 19.
    Millberg M, Nilsson E, Thid R, Jantsch A (2004) Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip. In: Proceedings of design, automation and test in Europe conference, February 2004Google Scholar
  20. 20.
    Murali S, Benini L, De Micheli G (2005) Mapping and physical planning of networks on chip architectures with quality-of-service guarantees. In: Proceedings of Asia and South Pacific design automation conference, January 2005Google Scholar
  21. 21.
    Nilsson E, Millberg M, Oberg J, Jantsch A (2003) Load distribution with the proximity congestion awareness in a network on chip. In: Proceedings of design, automation and test in Europe conference, March 2003Google Scholar
  22. 22.
    Paganini F, Doyle J, Low S (2001) Scalable laws for stable network congestion control. In: Proceedings of IEEE conference on decision and control, December 2001Google Scholar
  23. 23.
    Park K, Willinger W (eds) (2000) Self-similar network traffic and performance evaluation. Wiley, New YorkGoogle Scholar
  24. 24.
    Peh L, Dally WJ (2001) A delay model for router micro-architectures. IEEE Micro 21(1):26–34Google Scholar
  25. 25.
    Pullini A, Angiolini F, Bertozzi D, Benini L (2005) Fault tolerance overhead in network-on-chip flow control schemes. In: Proceedings of symposium on integrated circuits and system design, September 2005Google Scholar
  26. 26.
    Qiu D, Shro BN (2004) A predictive flow control mechanism to provide QoS and efficient network utilization. IEEE Trans Network 12(1):73–84Google Scholar
  27. 27.
    Radulescu A et al (2005) An efficient on-chip ni offering guaranteed services, shared-memory abstraction, and flexible network configuration. IEEE Trans Comput Aided Des Integr Circ Syst 24(1):4–17CrossRefGoogle Scholar
  28. 28.
    Smai A, Thorelli L (1998) Global reactive congestion control in multicomputer networks. In: Proceedings of the fifth international conference on high performance computing , December 1998Google Scholar
  29. 29.
    Thottethodi M, Lebeck AR, Mukherjee SS (2001) Self-tuned congestion control for multiprocessor networks. In: Proceedings of the 7th international symposium on high-performance computer architecture, January 2001Google Scholar
  30. 30.
    Varatkar G, Marculescu R (2004) On-chip traffic modeling and synthesis for MPEG-2 video applications. IEEE Trans VLSI 12(1):108–119CrossRefGoogle Scholar
  31. 31.
    Zeferino CA, Santo FME, Susin AA (2004) Paris: a parameterizable interconnect switch for networks-on-chip. In: Proceedings of symposium on integrated circuits and systems design, September 2004Google Scholar

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.Intel CorporationHillsboroUSA
  2. 2.Department of Electrical and Computer EngineeringCarnegie Mellon UniversityPittsburghUSA

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