NoC Performance Analysis

  • Umit Y. Ogras
  • Radu Marculescu
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 184)


Traditionally, performance evaluation of networks-on-chip (NoC) is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters can affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. This chapter presents a mathematical model for on-chip routers and utilize this new model for NoC performance analysis. The model presented in this chapter can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop. The accuracy of our approach and its practical use is illustrated through extensive simulation results.


  1. 1.
    Bertsekas D, Gallager R (1992) Data networks. Prentice Hall, Upper Saddle RiverMATHGoogle Scholar
  2. 2.
    Dally WJ (1990) Performance analysis of k-ary n-cube interconnection networks. IEEE Trans Comput 39(6):775–785MathSciNetCrossRefGoogle Scholar
  3. 3.
    Dielissen J, Radulescu A, Goossens K, Rijpkema E (2003) Concepts and implementation of the Philips network-on-chip. IP-based SoC DesignGoogle Scholar
  4. 4.
    Draper J, Ghosh J (1994) A comprehensive analytical model for wormhole routing in multicomputer systems. J Parallel Distrib Comput 23(2):202–214CrossRefGoogle Scholar
  5. 5.
    Guan W, Tsai W, Blough D (1993) An analytical model for wormhole routing in multicomputer interconnection networks. In: Proceedings of international parallel processing symposium, April (1993)Google Scholar
  6. 6.
    Guz Z, Walter I, Bolotin E, Cidon I, Ginosar R, Kolodny A (2006) Efficient link capacity and QoS design for wormhole network-on-chip. In: Proceedings of design, automation and test in Europe conference, March (2006)Google Scholar
  7. 7.
    Hu P, Kleinrock L (1997) An analytical model for wormhole routing with finite size input buffers. In: 15th international teletraffic congress, June (1997)Google Scholar
  8. 8.
    Hu J, Marculescu R (2005) Energy- and performance-aware mapping for regular NoC architectures. IEEE Trans Comput Aided Des Integr Circuits Syst 24(4):551–562CrossRefGoogle Scholar
  9. 9.
    Hu J, Ogras UY, Marculescu R (2006) System-level buffer allocation for application-specific networks-on-chip router design. IEEE Trans Comput Aided Des Integr Circuits Syst 25(12):2919–2933CrossRefGoogle Scholar
  10. 10.
    Lieverse P, Van Der Wolf P, Vissers K, Deprettere E (2001) A methodology for architecture exploration of heterogeneous signal processing systems. J VLSI Signal Process Syst Signal Image Video Technol 29(3):197–206Google Scholar
  11. 11.
    Marculescu R, Ogras UY, Peh L, Jerger NE, Hoskote Y (2009) Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives. IEEE Trans Comput Aided Des Integr Circuits Syst 28(1):3–21CrossRefGoogle Scholar
  12. 12.
    Millberg M, Nilsson E, Thid R, Jantsch A (2004) Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip. In: Proceedings of design, automation and test in Europe conference, Feb (2004)Google Scholar
  13. 13.
    Murali S, De Micheli G (2004) Bandwidth-constrained mapping of cores onto NoC architectures. In: Proceedings of design, automation and test in Europe conference, Feb (2004)Google Scholar
  14. 14.
    Ogras UY, Marculescu R (2006) “It’s a small world after all”: NoC performance optimization via long-range link insertion. IEEE Trans Very Large Scale Integr Syst Special Sect Hardw/Softw Codesign Syst Synth 14(7):693–706Google Scholar
  15. 15.
    Ogras UY, Bogdan P, Marculescu R (2010) An analytical approach for network-on-chip performance analysis. In: IEEE transaction on computer-aided design of integrated circuits and systems (TCAD), vol 29, Issue 12, Dec (2010)Google Scholar
  16. 16.
    Ould-Khaoua M, Sarbazi-Azad H (2001) An analytical model of adaptive wormhole routing in hypercubes in the presence of hot spot traffic. IEEE Trans Parallel Distrib Syst 12(3):283–292Google Scholar
  17. 17.
    Pande PP, Grecu C, Jones M, Ivanov A, Saleh R (2005) Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans Comput 54(8):1025–1040CrossRefGoogle Scholar
  18. 18.
    Ross S (2006) Simulation. Elsevier Academic Press, New YorkMATHGoogle Scholar
  19. 19.
    Strang G (2009) Introduction to linear algebra, 4th edn. Wellesley-Cambridge Press, WelleseleyGoogle Scholar
  20. 20.
    Varatkar G, Marculescu R (2004) On-chip traffic modeling and synthesis for MPEG-2 video applications. IEEE Trans VLSI 12(1):108–119CrossRefGoogle Scholar
  21. 21.
    Wang H, Zhu X, Peh L, Malik S (2002) Orion: a power-performance simulator for interconnection networks. In: Proceedings of annual international symposium on microarchitecture, Nov (2002)Google Scholar
  22. 22.
    Worm_Sim: a cycle accurate simulator for Networks-on-Chip.

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.Intel CorporationHillsboroUSA
  2. 2.Department of Electrical and Computer EngineeringCarnegie Mellon UniversityPittsburghUSA

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