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NoC Performance Analysis

  • Umit Y. Ogras
  • Radu Marculescu
Chapter
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 184)

Abstract

Traditionally, performance evaluation of networks-on-chip (NoC) is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters can affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. This chapter presents a mathematical model for on-chip routers and utilize this new model for NoC performance analysis. The model presented in this chapter can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop. The accuracy of our approach and its practical use is illustrated through extensive simulation results.

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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.Intel CorporationHillsboroUSA
  2. 2.Department of Electrical and Computer EngineeringCarnegie Mellon UniversityPittsburghUSA

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