Adders

  • Jean-Pierre Deschamps
  • Gustavo D. Sutter
  • Enrique Cant
Chapter
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 149)

Abstract

Addition is a primitive operation for most arithmetic functions, so that FPGA vendors have dedicated a particular attention to the design of optimized adders. As a consequence, in many cases the synthesis tools are able to generate fast and cost-effective adders from simple VHDL expressions. Only in the case of relatively long operands can it be worthwhile to consider more complex structures such as carry-skip, carry-select and logarithmic adders.

Keywords

Critical Path Full Adder FPGA Implementation Half Adder Significant Binary Digit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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    Deschamps JP, Bioul G, Sutter G (2006) Synthesis of arithmetic circuits. Wiley, New YorkGoogle Scholar

Copyright information

© Springer Science+Business Media Dordrecht 2012

Authors and Affiliations

  • Jean-Pierre Deschamps
    • 1
  • Gustavo D. Sutter
    • 2
  • Enrique Cant
    • 1
  1. 1.University Rovira i VirgiliTarragonaSpain
  2. 2.School of Computer EngineeringUniversidad Autonoma de MadridMadridSpain

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