Abstract
Partial Reconfiguration (PR) is the ability to change a portion (the reconfigurable partition) of the device without disturbing the normal operation of the rest (the static partition). A typical PR application is a reconfigurable coprocessor which switches the configuration of the reconfigurable partition at run-time when required by the application. The main advantage is the ability to map different coprocessor configurations in the reconfigurable partition in a time-multiplexed way, reducing the required area.
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References
Xilinx (2011a) Partial reconfiguration user’s guide (UG702)
Xilinx (2010a) Virtex-5 FPGA configuration user guide (UG191)
Avnet (2009) Virtex-5 LX evaluation kit. User guide
Xilinx (2010b) Virtex-5 FPGA user guide (UG190)
Xilinx (2011b) LogiCORE IP XPS HWICAP (DS586)
Xilinx (2010c) LogiCORE IP XPS multi-channel external memory controller (DS575)
Numonyx (2007) NumonyxTM embedded flash memory J3 v.D datasheet
Xilinx (2010d) XST user guide for virtex-4, virtex-5, spartan-3 and newer CPLD devices (UG627)
Xilinx (2011d) Data2MEM user guide (UG658)
Xilinx (2011c) Command line tools user guide (UG628)
PldTool (2010) Xilinx BIT bitstream files. http://www.pldtool.com/pdf/fmt_xilinxbit.pdf. Accessed July 2011
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© 2012 Springer Science+Business Media Dordrecht
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Deschamps, JP., Sutter, G.D., Cantó, E. (2012). Partial Reconfiguration on Xilinx FPGAs. In: Guide to FPGA Implementation of Arithmetic Functions. Lecture Notes in Electrical Engineering, vol 149. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-2987-2_16
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DOI: https://doi.org/10.1007/978-94-007-2987-2_16
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