Abstract
This research proposes a new embedded translation look-aside buffer (TLB) structure that can reduce the power consumption effectively by using simple hardware control logics. The proposed TLB structure is constructed as two fully associative TLBs and one of the two TLBs is selectively accessed by the dynamic selection method. It is shown that on-chip power consumption of the proposed TLB can be reduced by around 42% comparing with the conventional fully associative TLBs with the same number of entries.
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References
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Lee, Jh. (2011). Control Mechanism for Low Power Embedded TLB. In: Park, J., Arabnia, H., Chang, HB., Shon, T. (eds) IT Convergence and Services. Lecture Notes in Electrical Engineering, vol 107. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-2598-0_50
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DOI: https://doi.org/10.1007/978-94-007-2598-0_50
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