In this chapter, it is shown all circuits that are needed to perform the measurement of the test circuits on wafer, as published in . First, the delay line that will produce the artificial skew between the FF clocks is discussed. Then the ring oscillator needed to calibrate the delay line is showed. The next step is the design of a shift register to reduce the number of inputs. Finally, we put it all together and show the final layout.
- 33.NEUBERGER, G.; KASTENSMIDT, F.; REIS, R.; WIRTH, G.; BREDERLOW, R.; PACHA, C. Statistical Characterization of Hold Time Violations in 130nm CMOS Technology. In: European Solid-State Circuits Conference, 32., 2006, Montreux. Proceedings… Piscataway: IEEE, 2006. p. 114–117.Google Scholar