Abstract
Parameter variability has always been an issue in integrated circuits. However, comparing with the size of devices, it is relatively increasing with technology evolution, as the device size shrinks in a larger scale than our control over them. Also, in the past, the variations were mostly due to imperfect process control, but now intrinsic atomistic variations become more important, as devices of atomic sizes are achieved. This parameter variation causes uncertainties in circuit design, as in timing, power dissipation, and others important properties. Figure 2.1 shows the technology scaling, to exemplify how small the devices are becoming. Approaching the atomic scale is very difficult to control the process, as only one atom can make a huge difference.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Ashan, I. et al. RTAdriven Intra-die Variations in Stage delay and Parametric Sensitivities for 65 nm Technology, in VLSI Symp. Tech. Dig., Honolulu, HI, 2006, pp. 170–171.
ASENOV, A. Personal Communication. Work presented at 3rd European Workshop on Ultimate Integration of Silicon – ULIS, 2002, Munich, Germany. Workshop without formal proceedings.
AUSSCHNITT, C. et al. Industrial Strength Lithography APC. In: AMM Conference, 2003. Proceedings… [S.l.: s.n.], 2003. p. 1–11.
BORKAR, S. Designing reliable systems from unreliable components: the challenges of transistor variability and degradation. IEEE Micro, New York, v. 25, n. 6, p. 10–16, Nov./Dec. 2005.
BRUNNER, T. A. et al. High NA Swing Curve Effects. In: Optical Microlithography, 14., 2001, Santa Clara, CA. Proceedings… [S.l.]: SPIE, 2001. p. 1050–1057.
BRUNNER, T. A. Why Optical Lithography Will Live Forever. Journal of Vaccum Science & Technology B: Microelectronics and Nanometer: processing, measurement, and phenomena, New York, v.21, n.6, p. 2632–2637, 2003.
FRANK, D. J.; WONG, H.-S. P. Simulation of Stochastic Doping Effects in Si MOSFETs. In: International Workshop on Computational Electronics, IWCE, 7., 2000. Proceedings… Glasgow: University of Glasgow, 2000.
FRANK, D. J. Power-Constrained CMOS Scaling Limits. IBM Journal on Res. Devel., Armonk, v. 46, n. 2/3, Mar./May 2002.
FRANK, D. J. Parameter Variations in Sub-100 nm CMOS Technology. In: Advanced Solid State Circuits Forum, ISSCC, 2004. Proceedings… [S.l.: s.n.], 2004.
KUHN, K.; KENYON, C.; KORNFELD, A.; LIU, M.; MAHESHWARI, A.; SHIW, W.; SIVAKUMAR, S.; TAYLOR, G.; VANderVOORN, P.; ZAWADZKI, K. Managing Process Variation in Intel's 45nm CMOS Technology. Intel Technology Journal, v. 12, n. 2, p. 93–110, 2008.
Liebmann, L. W. et al. TCAD Development for Lithography Resolution Enhancement, IBM J. Res. Develop., vol. 45, no. 5, pp. 651–665, Sep. 2001.
Najm, F. N. “On the Need for Statistical Timing Analysis”, Proc. Design Automation Conference (DAC), pp. 764–765, 2005.
ROHRER, N. J. Introduction to Statistical Variation and Techniques for Design Optimization. Personal Communication, Tutorial presented at International Solid-State Circuits Conference, ISSCC, 2006.
Saxena, S. et al. Variation in Transistor Performance and Leakage in Nanometer-Scale Technologies”, IEEE Transactions on Electron Devices, Jan. 2008, Vol 55 Issue 1, pp. 131–144.
Springer, S. K. et al. Modeling of Variation in Submicrometer CMOS ULSI technologies, IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2168–2178, Sep. 2006.
van der Lann, H. et al. “Etch, Reticle, and Track CD Fingerprint Corrections with Local Dose Compensation”, Proc. SPIE, vol. 5755, pp. 107–118, 2005.
Visweswariah, C. Statistical Analysis and Design of Digital Integrated Circuits. Invited Presentation at EDA Forum, 2005, Hannover, Germany.
Wong, A. K. Resolution Enhancement Techniques in Optical Lithography. Bellingham, WA: SPIE Press, 2001.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2014 Springer Science+Business Media Dordrecht
About this chapter
Cite this chapter
Neuberger, G., Wirth, G., Reis, R. (2014). Process Variability. In: Protecting Chips Against Hold Time Violations Due to Variability. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-2427-3_2
Download citation
DOI: https://doi.org/10.1007/978-94-007-2427-3_2
Published:
Publisher Name: Springer, Dordrecht
Print ISBN: 978-94-007-2426-6
Online ISBN: 978-94-007-2427-3
eBook Packages: EngineeringEngineering (R0)