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The Implementation of Face Detection Algorithm AdaBoost Based in the Embedded System

Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 113)

Abstract

To solve the real-time problem of face detection, for the realization bottleneck of AdaBoost pure software algorithm, FPGA-based hardware acceleration platform strategy is proposed, using pipeline processing technology to achieve rapid calculation of integral image. Using PowerPC 405 processor VIrtex TM II Pro platform FPGA in the experiment, under the conditions of the size of the input image 352 × 288 pixels, detection speed reaches 50 frames per second; detection rate was 98%, false detection rate of about 1%, and thus achieving the requirement of real-time face detection.

Keywords

Detection Algorithm Hardware acceleration 

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Copyright information

© Springer Science+Business Media B.V. 2012

Authors and Affiliations

  1. 1.Henan Institute of Science and TechnologyXinxiangChina

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