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A 12b 2.9 GS/s DAC with IM3<–60 dBc Beyond 1 GHz in 65 nm CMOS

  • K. Bult
  • C.-H. Lin
  • F. van der Goes
  • J. Westra
  • J. Mulder
  • Y. Lin
  • E. Arslan
  • E. Ayranci
  • X. Liu
Chapter

Abstract

A 12b 2.9GS/s current-steering DAC implemented in 65 nm CMOS is presented, with an IM3 < −60dBc beyond 1 GHz while driving a 50 Ω load with an output swing of 2.5Vppd and dissipating a power of 188 mW. The SFDR measured at 2.9 GS/s is better than 60 dB beyond 340 MHz while the SFDR measured at 1.6 GS/s is better than 60 dB beyond 440 MHz. The increase in performance at high-frequencies, compared to previously published results, is mainly obtained by adding local cascodes on top of the current-switches with “always-ON” biasing.

Keywords

Current Source Parasitic Capacitance Output Impedance Switching Capacitor Output Swing 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media B.V. 2012

Authors and Affiliations

  • K. Bult
    • 1
  • C.-H. Lin
    • 2
  • F. van der Goes
    • 1
  • J. Westra
    • 1
  • J. Mulder
    • 1
  • Y. Lin
    • 1
  • E. Arslan
    • 1
  • E. Ayranci
    • 1
  • X. Liu
    • 1
  1. 1.Broadcom Netherlands BVBunnikThe Netherlands
  2. 2.Broadcom CorporationIrvineUSA

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