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Considerations for Cost-Efficient Calibration of Scaled ADCs

  • Marian Verhelst
  • Erkan Alpman
  • Hasnain Lakdawala
Chapter

Abstract

Observed ADC area and power scaling do not seem to follow the trends predicted using pure technology scaling arguments. A cubic improvement in area and power with gate length is observed in literature, which has been enabled by migration towards more and more capacitor-based ADC architectures, and the introduction of digitally-assisted performance enhancement strategies to overcome component mismatch. This paper assesses these trends, and discusses the most relevant enhancement strategies for mismatch-limited ADCs. Trade-off analysis between mismatch compensation in the analog domain (digitally assisted trimming, possibly in combination with up-scaling) vs. the digital domain (digital post-distortion) is required. The increasing use of digitally enhanced ADC architectures proves to be the main driver for the observed improvement in area and power with scaling.

Keywords

Power Consumption Flicker Noise Power Penalty Enhancement Strategy Digital Domain 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media B.V. 2012

Authors and Affiliations

  • Marian Verhelst
    • 1
  • Erkan Alpman
    • 1
  • Hasnain Lakdawala
    • 1
  1. 1.Intel Labs – Radio Integration ResearchHillsboroUSA

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