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Considerations for Cost-Efficient Calibration of Scaled ADCs

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Analog Circuit Design

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Abstract

Observed ADC area and power scaling do not seem to follow the trends predicted using pure technology scaling arguments. A cubic improvement in area and power with gate length is observed in literature, which has been enabled by migration towards more and more capacitor-based ADC architectures, and the introduction of digitally-assisted performance enhancement strategies to overcome component mismatch. This paper assesses these trends, and discusses the most relevant enhancement strategies for mismatch-limited ADCs. Trade-off analysis between mismatch compensation in the analog domain (digitally assisted trimming, possibly in combination with up-scaling) vs. the digital domain (digital post-distortion) is required. The increasing use of digitally enhanced ADC architectures proves to be the main driver for the observed improvement in area and power with scaling.

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References

  1. Kindly confirm the inserted conference locations in the following references: [1, 3, 5, 15, 17, 19–21, 23, 25–26, 30, 32–33, 35–36]. P. Scholtens, D. Smola, M. Vertregt, Systematic power reduction and performance analysis of mismatch limited ADC designs, in Proceedings of ISPED, Bordeaux, Aug 2005, pp. 78–83

    Google Scholar 

  2. Kindly confirm the updated details in Murmann (2006) and Rabaey et al. (2003). B. Murmann, Limits on ADC power dissipation, in Analog Circuit Design, ed. by A.H.M. van Roermund, H. Casier, M. Steyaert (Springer, Dordrecht, 2006), pp. 351–367

    Chapter  Google Scholar 

  3. Y. Chiu, B. Nikolic, P.R. Gray, Scaling of analog-to-digital converters into ultra-deep-submicron CMOS, in Proceedings of IEEE CICC, San Jose, 2005, pp. 375–382

    Google Scholar 

  4. Kindly confirm the updated journal title in the reference “Uyttenhove (2002)” and “Vertregt et al. (2003)”. K. Uyttenhove, M. Steyaert, Speed–power–accuracy tradeoff in high-speed CMOS ADCs. IEEE Trans. Circuits Syst. (CAS-II) 49(4), 280–287 (2002)

    Article  Google Scholar 

  5. P. Kinget, M. Steyaert, Impact of transistor mismatch on the speed-accuracy-power trade-off of analog CMOS circuits, in Proceedings of IEEE CICC, Rochester, 1988, pp. 333–336

    Google Scholar 

  6. M. Pelgrom, A. Duinmaijer, A. Welbers, Matching properties of MOS transistors. IEEE J. Solid-State Circuits 24(5), 1433–1440 (1989)

    Article  Google Scholar 

  7. P. Kinget, Device mismatch and tradeoffs in the design of analog circuits. IEEE J. Solid-State Circuits 40(6), 1212–1224 (2005)

    Article  Google Scholar 

  8. P. Nikaeen, B. Murmann, Digital compensation of dynamic acquisition errors at the front-end of high-performance A/D converters. IEEE J. Sel. Top. Signal Process. 3(3), 499–508 (2009)

    Article  Google Scholar 

  9. A. Abo, P. Gray, A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE J. Solid-State Circuits 34(4), 599–606 (1999)

    Article  Google Scholar 

  10. Kindly confirm the inserted publisher location in the reference “Laker (1994)”. K. Laker, W. Sansen, Design of Analog Integrated Circuits and Systems (McGraw-Hill, New York, 1994)

    Google Scholar 

  11. P. Woerlee, M. Knitel, R. van Langevelde, D. Klaassen, L. Tiemeijer, A. Scholten, A. Zegers-van Duijnhoven, RF-CMOS performance trends. IEEE Trans. Electron. Devices 48(8), 1776–1782 (2001)

    Article  Google Scholar 

  12. C. Diaz, D. Tang, J. Sun, CMOS technology for MS/RF SoC. IEEE Trans. Electron. Devices 50(3), 557–566 (2003)

    Article  Google Scholar 

  13. Q. Huang, F. Piazza, P. Orsatti, T. Ohguro, The impact of scaling down to deep submicron on CMOS RF circuits. IEEE J. Solid-State Circuits 33(7), 1023–1036 (1998)

    Article  Google Scholar 

  14. M. Vertregt, P. Scholtens, Scalable high-speed analog circuit design, in Analog Circuit Design, ed. by M. Steyaert, J.H. Huijsing, A.H.M. van Roermund (Kluwer, Boston, 2003), pp. 3–21

    Chapter  Google Scholar 

  15. C.-H. Jan et al., RF CMOS technology scaling in high-k/metal gate era for RF SoC (System-on-chip) applications, in Proceedings of IEEE IEDM, 2010, San Francisco, 2010, pp. 27.2.1

    Google Scholar 

  16. International Technology Roadmap for Semiconductors, 2009 edition: www.16.net/Links/200916/Home2009.htm

  17. B. Murmann, A/D converter trends: power dissipation, scaling and digitally assisted architectures, in Proceedings of IEEE CICC, 2008, San Jose, 2008, pp. 105–112

    Google Scholar 

  18. B. Murmann, ADC performance survey 1997–2010, [Online]. Available: www.stanford.edu/~murmann/adcsurvey.html

  19. P. Malla, H. Lakdawala, K. Kornegay, K. Soumyanath, A 28 mW spectrum-sensing reconfigurable 20 MHz 72 dB-SNR 70 dB-SNDR DT ΔΣ ADC for 802.11n/WiMAX receivers, in Proceedings of IEEE ISSCC, 2008, San Francisco, 2008, pp. 496–497

    Google Scholar 

  20. M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, B. Nauta, A 1.9 μW 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC, in IEEE ISSCC, 2008, San Francisco, 2008, pp. 244–245

    Google Scholar 

  21. H. Chung, A. Rylyakov, Z. Toprak Deniz, J. Bulzacchelli, G.-Y. Wei, D. Friedman, A 7.5-GS/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65 nm CMOS, in Proceedings of Symposium on VLSI Circuits, 2009, Kyoto, 2009, pp. 268–269

    Google Scholar 

  22. B. Murmann, Digitally assisted analog circuits. IEEE Micro 26(2), 38–47 (2006)

    Article  Google Scholar 

  23. B. Murmann, C. Vogel, H. Koeppl, Digitally enhanced analog circuits: system aspects, in Proceedings of ISCAS, 2008, Seattle, 2008, pp. 560–563

    Google Scholar 

  24. R. van de Plassche, A sigma-delta modulator as an A/D converter. IEEE TCAS 25(7), 510–514 (1978)

    Google Scholar 

  25. S. Weaver, B. Hershberg, D. Knierim, U. Moon, A 6b stochastic flash analog-to-digital converter without calibration or reference ladder, in IEEE ASSCC, 2008, Fukuoka, 2008, pp. 373–376

    Google Scholar 

  26. L. Pileggi, G. Keskin, X. Li, K. Mai, J. Proesel, Mismatch analysis and statistical design at 65 nm and below, in IEEE CICC 2008, San Jose, 2008, pp. 9–12

    Google Scholar 

  27. M. Flynn, C. Donovan, L. Sattler, Digital calibration incorporating redundancy of flash ADCs. IEEE Trans. Circuits Syst. CAS-II 50(5), 205–213 (2003)

    Article  Google Scholar 

  28. B. Verbruggen, J. Craninckx, M. Kuijk, P. Wambacq, G.V. der Plas, A 2.2 mW 1.75 GS/s 5 bit folding flash ADC in 90 nm digital CMOS. IEEE J. Solid-State Circuits 44(3), 874–882 (2009)

    Article  Google Scholar 

  29. D.C. Daly, A.P. Chandrakasan, A 6-bit, 0.2 V to 0.9 V highly digital flash ADC With comparator redundancy. IEEE J. Solid-State Circuits 44(11), 3030–3038 (2009)

    Article  Google Scholar 

  30. G.V. der Plas, S. Decoutere, S. Donnay, A 0.16pJ/conversion-Step 2.5 mW 1.25GS/s 4b ADC in a 90 nm digital CMOS process, in IEEE ISSCC, 2006, San Francisco, 2008, p. 2310

    Google Scholar 

  31. J. Rabaey, A. Chandrakasan, B. Nikolic (eds.), Digital Integrated Circuits, 2nd edn. (Prentice Hall, Upper Saddle River, 2003)

    Google Scholar 

  32. C. Grace, P. Hurst, S. Lewis, A 12b 80MS/s pipelined ADC with bootstrapped digital calibration, in IEEE ISSCC, 2004, San Francisco, 2004, p. 460

    Google Scholar 

  33. C. Vogel, S. Saleem, S. Mendel, Adaptive blind compensation of gain and timing mismatches in M-channel time-interleaved ADCs, in Proceedings of IEEE ICECS, Malta, Sept 2008, pp. 49–52

    Google Scholar 

  34. Y. Oh, B. Murmann, System embedded ADC calibration for OFDM receivers. IEEE Trans. Circuits Syst. CAS-I 53(8), 1693–1703 (2006)

    Article  Google Scholar 

  35. E. Alpman, H. Lakdawala, R. Carley, K. Soumyanath, A 1.1 V 50 mW 2.5GS/s 7b time-interleaved C-2C SAR ADC in 45 nm LP digital CMOS, in IEEE ISSCC, 2009, San Francisco, 2009, pp. 76–77

    Google Scholar 

  36. S. Iyer et al., A 0.5 mm2 integrated capacitive vibration sensor with sub-10 zF/rt-Hz noise floor, in IEEE CICC, 2005, San Jose, 2005, pp. 93–96

    Google Scholar 

  37. Y.-C. Jenq, Digital spectra of nonuniformly sampled signals: a robust sampling time offset estimation algorithm for ultra high-speed waveform interleaving. IEEE Trans. Instrum. Meas. 39(1), 71–75 (1990)

    Article  Google Scholar 

  38. C. Farrow, A continuously variable digital delay element. Proc. IEEE ISCAS 3, 2641–2645 (1988)

    Google Scholar 

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Authors and Affiliations

  1. Intel Labs – Radio Integration Research, 2111 NW 25th Ave, Hillsboro, OR, USA

    Marian Verhelst, Erkan Alpman & Hasnain Lakdawala

Authors
  1. Marian Verhelst
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  2. Erkan Alpman
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  3. Hasnain Lakdawala
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Correspondence to Marian Verhelst .

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Editors and Affiliations

  1. , Dept. Elektrotechniek, K.U.Leuven, Kardinaal Mercierlaan 94, HEVERLEE, B-3001, Belgium

    Michiel Steyaert

  2. Electrical Engineering, Mixed-signal Microelectronics Group, Technical University Eindhoven, Eindhoven, 5600 MB, Netherlands

    Arthur van Roermund

  3. , Department of Physics, University of Milan-Bicocca, Milan, Italy

    Andrea Baschirotto

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Verhelst, M., Alpman, E., Lakdawala, H. (2012). Considerations for Cost-Efficient Calibration of Scaled ADCs. In: Steyaert, M., van Roermund, A., Baschirotto, A. (eds) Analog Circuit Design. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-1926-2_5

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  • DOI: https://doi.org/10.1007/978-94-007-1926-2_5

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  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-94-007-1925-5

  • Online ISBN: 978-94-007-1926-2

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