3-D ICs for Low Power/Energy

  • Kyungsu Kang
  • Chong-Min Kyung
  • Sungjoo Yoo


System-level integration is expected to gradually become a reality because of continuing aggressive device scaling (for 2-D dies) and launch of 3-D integration technology. Thus, chip power density, which is already a serious issue due to its exponential increase every year, and the related thermal issues in 3-D IC chips, especially microprocessors, may pose serious design problems unless properly addressed in advance. Such temperature-related problems include material as well as electrical reliability, leakage power consumption and possible regenerative phenomena such as avalanche breakdown, and the resultant manufacturing/packaging costs. In this chapter, various temperature-aware power management methods, e.g., voltage and frequency scaling, power gating, and thread scheduling, are introduced, with a special emphasis on performance improvement and energy-saving features.


Heat Sink Critical Speed Power Budget Negative Bias Temperature Instability Dynamic Voltage Frequency Scaling 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  1. 1.KAISTDaejeonRepublic of Korea
  2. 2.POSTECHPohangRepublic of Korea

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