3-D ICs for Low Power/Energy

Abstract

System-level integration is expected to gradually become a reality because of continuing aggressive device scaling (for 2-D dies) and launch of 3-D integration technology. Thus, chip power density, which is already a serious issue due to its exponential increase every year, and the related thermal issues in 3-D IC chips, especially microprocessors, may pose serious design problems unless properly addressed in advance. Such temperature-related problems include material as well as electrical reliability, leakage power consumption and possible regenerative phenomena such as avalanche breakdown, and the resultant manufacturing/packaging costs. In this chapter, various temperature-aware power management methods, e.g., voltage and frequency scaling, power gating, and thread scheduling, are introduced, with a special emphasis on performance improvement and energy-saving features.

Keywords

Heat Sink Critical Speed Power Budget Negative Bias Temperature Instability Dynamic Voltage Frequency Scaling 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Transistor counts on Wikipedia [Online]. Available http://en.wikipedia.org/wiki/Transistor_count
  2. 2.
    Benini, L., Micheli, G.D.: Networks on chips: a new SoC paradigm. Computer 35(1), 70–78 (2002) CrossRefGoogle Scholar
  3. 3.
    Xie, Y.: Processor architecture design using 3D integration technology. In: Proc. Int. Conf. on VLSI Design, pp. 446–451 (2010) Google Scholar
  4. 4.
    Joyner, J.W., Zarkesh-Ha, P., Meindl, J.D.: A stochastic global net-length distribution for a three-dimensional system-on-a-chip (3D-SoC). In: Proc. IEEE Int. ASIC/SOC Conf, pp. 147–151 (2001) Google Scholar
  5. 5.
    Loh, G., Xie, Y., Black, B.: Processor design in 3D die-stacking technologies. IEEE MICRO 27(3), 31–48 (2007) CrossRefGoogle Scholar
  6. 6.
    Zia, A., et al.: A 3-D cache with ultra-wide data bus for 3-D processor-memory integration. IEEE Trans. Very Large Scale Integr. 18(6), 967–977 (2010) CrossRefGoogle Scholar
  7. 7.
    Kumar, A., et al.: HybDTM: a coordinated hardware-software approach for dynamic thermal management. In: Proc. DAC, pp. 548–553 (2006) Google Scholar
  8. 8.
    Rao, R., et al.: An optimal analytical solution for processor speed control with thermal constraints. In: Proc. ISLPED, pp. 292–297 (2006) Google Scholar
  9. 9.
    Yang, J., et al.: Dynamic thermal management through task scheduling. In: Proc. Int. Symp. ISPASS, pp. 191–201 (2008) Google Scholar
  10. 10.
    Zhu, C., et al.: Three-dimensional chip-multiprocessor runtime thermal management. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 27(8), 1479–1492 (2008) CrossRefGoogle Scholar
  11. 11.
    Isci, C., et al.: An analysis of efficient multi-core global power management policies: maximizing performance for a given power budget. In: Proc. Int. Symp. Microarchitecture, Dec. 2006, pp. 347–358 (2006) Google Scholar
  12. 12.
    Kreith, F.: The CRC Handbook of Thermal Engineering, pp. 2.1–2.92. CRC Press, Boca Raton (2000) MATHGoogle Scholar
  13. 13.
    Yang, Y., et al.: Adaptive multi-domain thermal modeling and analysis for integrated circuit synthesis and design. In: Proc. ICCAD, Nov. 2006, pp. 575–582 (2006) CrossRefGoogle Scholar
  14. 14.
    Zhou, X., et al.: Thermal-aware task scheduling for 3D multi-core processors. IEEE Trans. Parallel Distrib. Syst. 21(1), 60–71 (2010) CrossRefGoogle Scholar
  15. 15.
    Li, T., John, L.K.: Runtime modeling and estimation of operating system power consumption. In: Proc. SIGMETRICS, pp. 160–171 (2003) Google Scholar
  16. 16.
    Chen, J.W., Dubois, M., Stenstrom, P.: Integrating complete-system and user-level performance/power simulators: the SimWattch approach. In: Proc. ISPASS, Mar. 2003, pp. 1–10 (2003) Google Scholar
  17. 17.
    Gomaa, M., Powell, M.D., Vijaykumar, T.N.: Heat-and-run: leveraging SMT and CMP to manage power density through the operating system. In: Proc. ASPLOS, Nov. 2004, pp. 260–270 (2004) Google Scholar
  18. 18.
    Performance Application Programming Interface [Online]. Available http://icl.cs.utk.edu/papi/
  19. 19.
    Corliss, G.: Which root does the bisection algorithm find? SIAM Rev. 325–327 (1977) Google Scholar
  20. 20.
    Lorch, J.R., Smith, A.J.: Improving dynamic voltage scaling algorithm with PACE. ACM SIGMETRICS Perform. Eval. Rev. 29(1), 50–61 (2001) CrossRefGoogle Scholar
  21. 21.
    Choi, K., Soma, R., Pedram, M.: Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 24(1), 18–28 (2005) CrossRefGoogle Scholar
  22. 22.
    Everett, H. III: Generalized Lagrange multiplier method for solving problems of optimum allocation of resources. Oper. Res. 11, 399–417 (1963) MathSciNetMATHCrossRefGoogle Scholar
  23. 23.
    Skadron, K., et al.: Temperature-aware microarchitecture: modeling and implementation. ACM Trans. Archit. Code Optim. 1, 94–125 (2004) CrossRefGoogle Scholar
  24. 24.
    Kang, K., Kim, J., Yoo, S., Kyung, C.-M.: Runtime power management of 3D multi-core architectures under peak power and temperature constraints. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 30(6), 905–918 (2011) CrossRefGoogle Scholar
  25. 25.
    Huang, W., et al.: HotSpot: a compact thermal modeling method for CMOS VLSI systems. IEEE Trans. Very Large Scale Integr. 14(5), 501–513 (2006) CrossRefGoogle Scholar
  26. 26.
    Bao, M., et al.: Temperature-aware voltage selection for energy minimization. In: Proc. DATE, pp. 1083–1086 (2008) CrossRefGoogle Scholar
  27. 27.
    Kang, K., Kim, J., Yoo, S., Kyung, C.-M.: Temperature-aware integrated DVFS and power gating for executing tasks with runtime distribution. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 29(9), 1381–1394 (2010) CrossRefGoogle Scholar
  28. 28.
    Yuan, L., et al.: Temperature-aware leakage minimization technique for real-time systems. In: Proc. ICCAD, pp. 761–764 (2006) CrossRefGoogle Scholar
  29. 29.
    Krantz, S., Kress, S., Kress, R.: Jensen’s Inequality. Birkhauser, Cambridge (1999) Google Scholar
  30. 30.
    Coskun, A.K., et al.: Dynamic thermal management in 3D multicore architectures. In: Proc. DATE, pp. 1410–1415 (2009) Google Scholar

Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  1. 1.KAISTDaejeonRepublic of Korea
  2. 2.POSTECHPohangRepublic of Korea

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