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Heterogeneous Reactive Architectures of Embedded Systems

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Embedded Systems Design Based on Formal Models of Computation
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Abstract

Long-term trend in semiconductor development has been integration of larger and larger systems on a single chip. It has been governed by Moore’s law in terms of integration capabilities and double increase of the number of transistors on a chip every 12–24 months. At the same time this has also led to the increasing raw computation power on a single chip. However, all those transistors can’t be used to achieve faster and more powerful processors due to architectural and power limitations. Rather, the development has taken another direction towards systems on chip which consists of many processors or processing elements, sometimes tens or hundreds of such elements, with a clear trend towards chips which will have thousands of processors. One of the main reasons for this trend is that those processors are simpler, easier to implement and work at lower frequencies than high performance processors, thus they are less power and energy demanding. However, the new approach, which is often referred to as multiple processor (or multiprocessor) systems on chip (MPSoC) faces many challenges. Among them most notable are related to the selection of the type of processing elements (e.g. general purpose vs. application-specific, uniform vs. heterogeneous), selection of interconnect structures and system architecture (e.g. networks on chip vs. circuit interconnect vs. buses), life-time of the processing elements (static or dynamic or reconfigurable), run-time support (operating systems or customized), design flow and tools support (e.g. traditional programming languages vs. concurrent languages). Many new architectures have emerged with a claim of their advantages over others in at least specific application domains. The new approaches are mostly based on concentration on certain features (e.g. architecture, run-time support or languages) but not many of them look at the big picture and design flow that will ensure more consistency and better linkages between those features.

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References

  1. G. Berry, G. Gonthier, The Esterel synchronous programming language: design, semantics, implementation. Sci. Comput. Program. 19(2), 87–152 (1992)

    Article  MATH  Google Scholar 

  2. D. Atienza et al., Network-on-Chip design and synthesis outlook. Integr. VLSI J. 41, 340–359 (2008)

    Article  Google Scholar 

  3. T. Bjerregaard, S. Mahadevan, A survey of research and practices of Network-on-Chip. ACM Comput. Surv. 38, 1–51 (2006)

    Article  Google Scholar 

  4. E. Salminen, A. Kulmala, T.D. Hamalainen, Survey of network-on-chip proposals, White paper, OCP-IP, Mar 2008

    Google Scholar 

  5. W. Hwu, Many-core computing: can compilers and tools do the heavy lifting?, in 9th International Forum on Embedded MPSoC and Multicore, MPSoC’09, 2009

    Google Scholar 

  6. Tensilica Xtensa processor, www.tensilica.com

  7. Intel, Single-chip Cloud Computer Overview, Intel Corporation (2010)

    Google Scholar 

  8. M. Schoeberl, Schedule memory access, not threads, in 10th International Forum on Embedded MPSoC and Multicore, MPSoC’10, 2010

    Google Scholar 

  9. H. Dutta et.al, Massively parallel processor architectures: a co-design approach, in Proceedings of the 3rd International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC), Montpellier, 18–20 June 2007, pp. 61–68

    Google Scholar 

  10. L. Bauer et. al., KAHRISMA: a multi-grained reconfigurable multicore architecture, in 10th International Forum on Embedded MPSoC and Multicore, MPSoC’10, 2010

    Google Scholar 

  11. D. Göhringer, M. Hübner, V. Schatz, J. Becker, Runtime adaptive multi-processor system-on-chip: RAMPSoC, in IEEE International Symposium on Parallel and Distributed Processing, 2008, pp. 1–7

    Google Scholar 

  12. Z. Salcic, D. Hui, P. Roop, M. Biglari-Abhari, REMIC – design of a reactive embedded microprocessor core, in Asia-South Pacific Design Automation Conference, Shanghai, Jan 2005

    Google Scholar 

  13. M.W.S. Dayaratne, P. Roop, Z. Salcic, Direct execution of Esterel using reactive microprocessors, synchronous languages, in Applications and Programming, SLAP 05, Edinburgh, Apr 2005

    Google Scholar 

  14. L.H. Yoon, P. Roop, Z. Salcic, F. Gruian, Compiling Esterel for direct execution, in Proceedings of the Conference on Synchronous Languages, Applications and Programming, SLAP 2006, Vienna, Mar 2006

    Google Scholar 

  15. Z. Salcic, D. Hui, P. Roop, M. Biglari-Abhari, HiDRA – a reactive multiprocessor architecture for heterogeneous embedded systems. Elsevier J. Microprocess. Microsyst. 30(2), 72–85 (2006)

    Article  Google Scholar 

  16. A. Malik, Z. Salcic, P. Roop, SystemJ compilation using the tandem virtual machine approach, in ACM Transactions on Design Automation of Electronic Systems (2009)

    Google Scholar 

  17. A. Malik, Z. Salcic, A. Girault, A. Walker, S.C. Lee, A customizable multiprocessor for globally asynchronous locally synchronous execution, in Proceedings of Java Technologies for Real-time and Embedded Systems, JTRES’09, Madrid, 2009, ACM

    Google Scholar 

  18. F. Gruian, P. Roop, Z. Salcic, I. Radojevic, SystemJ approach to system-level design, in Proceedings of Methods and Models for Co-Design Conference, Memocode 2006, Napa Valley, 2006, Piscataway, (IEEE Cat. No. 06EX1398). IEEE. 2006, pp. 149–58

    Google Scholar 

  19. A. Malik, Z. Salcic, P. Roop, A. Girault, SystemJ: a GALS language for system level design. Elsevier J. Comput. Lang. Syst. Struct. 36(4), 317–344 (2010). doi:10.1016/j.cl.2010.01.001

    Google Scholar 

  20. Z. Salcic, P. Roop, M. Biglari-Abhari, A. Bigdeli, REFLIX: a framework of a novel processor core for reactive embedded applications. Elsevier J. Microprocess. Microsyst. 28, 13–25 (2004)

    Article  Google Scholar 

  21. X. Li, R. von Hanxleden, The Kiel Esterel Processor – a semi-custom, configurable reactive processor, in Synchronous Programming – SYNCHRON’04, ser. Dagstuhl Seminar Proceedings, no. 04491, ed. by S.A. Edwards, N. Halbwachs, R.v. Hanxleden, T. Stauner (Schloss Dagstuhl, Germany, 2005)

    Google Scholar 

  22. S. Yuan, S. Andalam, L.H. Yoong, P. Roop, Z. Salcic, STARPro – a new multithreaded direct execution platform for Esterel. EURASIP J. Embed. Syst. in press (accepted 5 Feb 2009)

    Google Scholar 

  23. P. Roop, Z. Salcic,S. Dayaratne, Towards direct execution of Esterel programs on reactive processors, in Embedded Software Conference, EMSOFT’04, Pisa, 27–29 Sept 2004

    Google Scholar 

  24. L. Yang, M. Biglari-Abhari, Z. Salcic, A power-efficient processor core for reactive embedded applications, in Proceedings of Asia-South Pacific Computer Architecture Conference, ASCAC, 2006

    Google Scholar 

  25. P. Petrov, A. Orailogulu, Low-power instruction bus encoding for embedded processors. IEEE Trans. Very Large Scale Integr. Syst. 12(8), 812–826 (2004)

    Article  Google Scholar 

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Correspondence to Ivan Radojevic .

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Radojevic, I., Salcic, Z. (2011). Heterogeneous Reactive Architectures of Embedded Systems. In: Embedded Systems Design Based on Formal Models of Computation. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-1594-3_7

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  • DOI: https://doi.org/10.1007/978-94-007-1594-3_7

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