A Scalable Bandwidth-Aware Architecture for Connected Component Labeling

  • Vikram Sampath Kumar
  • Kevin Irick
  • Ahmed Al Maashri
  • Vijaykrishnan Narayanan
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 105)


This chapter discusses the design and implementation of a streaming-based Connected Component Labeling architecture. The architecture implements a scalable processor, which can be tuned to match the available I/O bandwidth on the computing platform that hosts the hardware. In addition, the chapter presents the hardware performance measurements when implemented on an FPGA platform.


Hardware Implementation Entry Register Connected Region Foreground Pixel Memory Subsystem 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



This work was supported in part by NSF awards #0702617 & #0916887, and a scholarship funding from the Government of the Sultanate of Oman.


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Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  • Vikram Sampath Kumar
    • 1
  • Kevin Irick
    • 1
  • Ahmed Al Maashri
    • 1
  • Vijaykrishnan Narayanan
    • 1
  1. 1.Microsystems Design Laboratory (MDL), Department of Computer Science and EngineeringThe Pennsylvania State UniversityUniversity ParkUSA

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