Abstract
This chapter introduces a methodology for fast and efficient Design Space Exploration during High Level Synthesis. Motivated by the fact that higher quality design solutions are delivered when a larger number of parameters are explored, we study an augmented instance of the design space considering the combined impact of loop-unrolling, operation chaining and resource allocation onto the final datapath. We propose an iterative design space partitioning exploration strategy based on the synergy of an exhaustive traversal together with an introduced heuristic one. The introduced heuristic is based on a gradient-based pruning technique which efficiently evaluates large portions of the solution space in a quick manner. We show that the proposed exploration approach delivers high quality results, with considerable reductions of the exploration’s runtime in respect to the fully exhaustive approach.
This research is partially supported by the E.C funded program MOSART IST-215244,Website:http://www.mosart-project.org/.
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Xydis, S., Pekmestzi, K., Soudris, D., Economakos, G. (2011). A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning. In: Voros, N., Mukherjee, A., Sklavos, N., Masselos, K., Huebner, M. (eds) VLSI 2010 Annual Symposium. Lecture Notes in Electrical Engineering, vol 105. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-1488-5_7
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DOI: https://doi.org/10.1007/978-94-007-1488-5_7
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