Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model

  • Naoya Onizawa
  • Tomoyoshi Funazaki
  • Atsushi Matsumoto
  • Takahiro Hanyu
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 105)


A performance-evaluation simulator, such as a cycle-accurate simulator, is a key tool for exploring appropriate asynchronous Network-on-Chip (NoC) architectures in early stages of VLSI design, but its accuracy is insufficient in practical VLSI implementation. In this paper, a highly accurate performance-evaluation simulator based on a delay-aware model is proposed for implementing an appropriate asynchronous NoC system. While the unit delay between circuit blocks at every pipeline stage is constant in the conventional cycle-accurate simulator, which causes poor accuracy, the unit delay between circuit blocks in the proposed approach is determined independently by its desirable logic function. The use of this "delay-aware" model makes it accurate to simulate asynchronous NoC systems. As a design example, a 16-core asynchronous Spidergon NoC system is simulated by the conventional cycle-accurate and the proposed simulator whose results, such as latency and throughput, are validated with a highly precise transistor-level simulation result. As a result, the proposed simulator achieves almost the same accuracy as one of the transistor-level simulators with the simulation speed comparable to the cycle-accurate simulator.



This research was supported by JST, CREST. This simulation is supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsys, Inc. and Cadence Design Systems, Inc.


  1. 1.
    Benini L, De Micheli G (2002) Networks on chips: a new SoC paradigm. IEEE Comput 35(1):70–78Google Scholar
  2. 2.
    Vangal S, Howard J, Ruhl G, Dighe S, Wilson H, Tschanz J, Finan D, Iyer P, Singh A, Jacob T, Jain S, Venkataraman S, Hoskote Y, Borkar N (2007) An 80-tile 1.28TFLOPS network-on-chip in 65 nm CMOS. In: IEEE ISSCC Digest of technical papers, pp 98–99 Feb 2007Google Scholar
  3. 3.
    Chapiro DM (1984) Globally-asynchronous locally-synchronous sysmtes. Ph.D. Thesis, Stanford University, Stanford, CA, Oct 1984Google Scholar
  4. 4.
    Lattard D, Beigne E, Clermidy F, Durand Y, Lemaire R, Vivet P, Berens F (2008) A recongurable baseband platform based on an asynchronous network-on-chip. IEEE J Solid-State Circuits 43(1):223–235CrossRefGoogle Scholar
  5. 5.
    Bakhouya M, Suboh S, Gaber J, El-Ghazawi T (2009) Analytical modeling and evaluation of on-chip interconnects using network calculus. In: The 2009 3rd ACM/IEEE international symposium on networks-on-chip, NOCS ’09, pp 74–79Google Scholar
  6. 6.
    Banerjee A, Wolkotte PT, Mullins RD, Moore SW, Smit GJM (2009) An energy and performance exploration of network-on-chip architectures. IEEE Trans Very Large Scale Integr VLSI Syst 17:319–329CrossRefGoogle Scholar
  7. 7.
    Loghi M, Angiolini F, Bertozzi D, Benini L, Zafalon R (2004) Analyzing on-chip communication in a MPSoC environment. In: Design, automation and test in Europe conference and exhibition, DATE ’ 04, vol. 2. pp 752–757Google Scholar
  8. 8.
    Wolkotte PT, Holzenspies PK, Smit GJM, (2007) Fast, accurate and detailed NoC simulations. In: The first international symposium on networks-on-chip, NOCS ’07, pp 323–332Google Scholar
  9. 9.
    Moadeli M, Shahrabi A, Vanderbauwhede W, Ould-Khaoua M (2007) An analytical performance model for the spidergon NoC. In: The 21st international conference on advanced information networking and applications, AINA ’07, pp 1014–1021Google Scholar
  10. 10.
    Beigne E, Clermidy F, Vivet P, Clouard A, Renaudin M (2005) An asynchronous NOC architecture providing low latency service and its multi-level design framework. In: The 11th IEEE international symposium on asynchronous circuits and systems, ASYNC ’05, pp 54–63Google Scholar
  11. 11.
    Bainbridge J, Furber S (2002) Chain: a delay-insensitive chip area interconnect. IEEE Micro 22(5):16–23CrossRefGoogle Scholar
  12. 12.
    Mizusawa K, Onizawa N, Hanyu T (2008) Power-aware asynchronous peer-to-peer duplex communication system based on multiple-valued one-phase signaling. IEICE Trans Electron E91-C(04)):581–588CrossRefGoogle Scholar
  13. 13.
    Otake Y, Onizawa N, Hanyu T (2009) High-performance asynchronous intra-chip communication link based on a multiple-valued current-mode single-track scheme. In: IEEE international symposium on circuits and systems, ISCAS ’09, pp 1000–1003Google Scholar
  14. 14.
    Sparsø J, Furber S (2001) Principles of asynchronous circuit design. Kluwer Academic Publisher, DordrechtGoogle Scholar
  15. 15.
    Ogras UY, Marculescu R (2007) Analytical router modeling for networks-on-chip performance analysis. In: Design, automation and test in Europe conference and exhibition, DATE ’07, pp 1–6 Google Scholar
  16. 16.
    Kahng AB, Li B, Peh L-S, Samadi K (2009) ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration. In: Design, automation and test in Europe conference and exhibition, DATE ’09, pp 423–428Google Scholar
  17. 17.
    Ling X, Chiu-Sing C (2007) A network-on-chip system-level simulation environment supporting asynchronous router. In: The 7th international conference on ASIC, ASICON ’07, pp 1241–1244Google Scholar
  18. 18.
    Shams M, Ebergen JC, Elmasry MI (1998) Modeling and comparing CMOS implementations of the C-element. IEEE Trans Very Large Scale Integr VLSI Syst 6(4):563–567CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  • Naoya Onizawa
    • 1
  • Tomoyoshi Funazaki
    • 1
  • Atsushi Matsumoto
    • 1
  • Takahiro Hanyu
    • 1
  1. 1.Research Institute of Electrical CommunicationTohoku UniversitySendaiJapan

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